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| cypress semiconductor corporation 198 champion court san jose , ca 95134 - 1709 408 - 943 - 2600 document number: 002 - 14779 rev. *f revised july 1, 2016 the following document contains information on cypress products. although the document is marked with the name broadcom , the company that originally developed the specification, cypress will continue to offer these pr oducts to new and existing customers. continuity of specifications there is no change to this document as a result of offering the device as a cypress product. any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. future revisions will occur when appropriate, and changes will be noted in a document history page. continuity of ordering part numbers cypress continues to support existing part numbers. to order these products , please use only the ordering part numbers listed in this document. for more information please visit our website at www .cypress.com or contact your local sales office for additional information about cypress pro ducts and services. our customers cypress is for true innovators C in companies both large and small. our customers are smart, aggressive, out - of - the - box thinkers who design and develop game - changing products that revolutionize their industries or create n ew industries with products and solutions that nobody ever thought of before. about cypress founded in 1982, cypress is the leader in advanced embedded system solutions for the worlds most innovative automotive, industrial, home automation and appliances, consumer electronics and medical products. cypresss programmable systems - on - chip, general - purpose microcontrollers, analog ics, wireless and usb - based connectivity solutions and reliable, high - performance memories help engineers design differentiated pro ducts and get them to market first. cypress is committed to providing customers with the best support and engineering resources on the planet enabling innovators and out - of - the - box thinkers to disrupt markets and create new product categories in record tim e. to learn more, go to www.cypress.com .
43362-ds106-r 5300 california avenue ? irvine, ca 92617 ? phone: 949-926-5000 ? fax: 949-926-5203 february 13, 2015 data sheet bcm43362 single-chip ieee 802.11? b/g/n mac/baseband/radio + sdio figure 1: bcm43362 system block diagram general description features the broadcom? bcm43362 single-chip device provides the highest level of integration for mobile and handheld wireless systems, featuring integrated ieee 802.11? b/g and handheld device class ieee 802.11n. it includes a 2.4 ghz wlan cmos power amplifier (pa) that meets the output power requirements of most handheld systems. an optional external low-noise amplifier (lna) and external pa are also supported. along with the integrated power amplifier, the bcm43362 also includes integrated transmit and receive baluns, further reducing the overall solution cost. host interface options include sdio v2.0 that can operate in 4b or 1b modes, and a generic gspi mode. utilizing advanced design techniques and process technology to reduce active and idle power, the bcm43362 is designed to address the needs of highly mobile devices that require minimal power consumption and compact size. it includes a power management unit that simplifies the system power topology and allows for operation directly from a rechargeable mobile platform battery while maximizing battery life. ? single-band 2.4 ghz ieee 802.11 b/g/n ? integrated wlan cmos power amplifier with internal power detector and closed-loop power control ? internal fractional-n pll enables the use of a wide range of reference clock frequencies ? supports ieee 802.15.2 external 3-wire and 4-wire coexistence schemes to optimize bandwidth utilization with other co-located wireless technologies such as bluetooth, zigbee, or bt smart. ? supports standard interfaces sdio v2.0 (50 mhz, 4-bit and 1-bit) and generic spi (up to 50 mhz) ? integrated arm cortex?-m3 cpu with on-chip memory enables running ieee 802.11 firmware that can be field-upgraded with future features. ? supports wmm?, wmm-ps, and wi-fi voice personal (upgradable to voice enterprise in the future) ? security: ? hardware wapi acceleration engine ? aes and tkip in hardware for faster data encryption and ieee 802.11i compatibility ? wpa?- and wpa2?- (personal) support for powerful encryption and authentication ? programmable dynamic power management ? supports battery voltage range from 2.3v to 4.8v supplies with internal switching regulator ? 1 kbit one-time programmable (otp) memory for storing board parameters ? 69-bump wlbga (4.52 mm x 2.92 mm, 0.4 mm pitch) t/r switch vio vbatt 2.4 ghz wlan tx 2.4 ghz wlan rx bcm43362 wlan host i/f wl_rst_n sdio/spi cbf coexistence interface system clock sleep clock revision history bcm43362 data sheet broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 2 broadcom confidential revision history revision date change description 43362-ds106-r 02/13/15 updated: ? removed ?preliminary? from the document type. 43362-ds105-r 04/07/14 updated: ? ieee 802.15.2 support for zigbee and bt smart on page 1. ? coexistence interfaces for zigbee and bt smart on page 11. deleted: ? ccxv(2, 3, 4, 5) proprietary protocols on page 11. 43362-ds104-r 02/17/12 updated: ? table 23: ?system power consumption,? on page 79 deleted: ? support for short gi mode in tx and rx 43362-ds103-r 9/1/11 updated: ? changed maximum battery voltage range from 5.5v to 4.8v. ? ?low-power shutdown? on page 20. ? table 8: ?wlbga signal descriptions,? on page 53. ? table 13: ?esd specifications,? on page 63. ? table 16: ?wlan 2.4 ghz receiver performance specifications,? on page 67. ? table 17: ?wlan 2.4 ghz transmitter performance specifications,? on page 70. ? table 18: ?general spurious emissions specifications,? on page 72. ? table 19: ?core buck regulator,? on page 73. ? table 20: ?3.3v ldo (ldo3p3),? on page 76. ? table 23: ?system power consumption,? on page 79. 43362-ds102-r 3/28/11 updated: ? table 6: ?gspi registers,? on page 34. ? table 11: ?absolute maximum ratings,? on page 62. ? table 14: ?recommended operating conditions and dc characteristics,? on page 64. ? table 19: ?core buck regulator,? on page 73. ? table 20: ?3.3v ldo (ldo3p3),? on page 76. broadcom ? , the pulse logo, connecting everything ? , and the connecting everything logo are among the trademarks of broadcom corporation and/or its affiliates in the united states, certain other countries and/or the eu. any other trademarks or trade names mentioned are the property of their respective owners. this data sheet (including, without limitation, the broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high-risk application. broadcom provides this data sheet ?as-is,? without warranty of any kind. broadcom disclaims all warranties, expressed and implied, including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non- infringement. broadcom corporation 5300 california avenue irvine, ca 92617 ? 2015 by broadcom corporation all rights reserved printed in the u.s.a. 43362-ds101-r 2/17/11 updated: ? lpo clock to lpo sleep clock throughout the document. ? figure 3: ?power topology,? on page 15. ? ?tcxo? on page 20. ? table 2: ?crystal oscillator and external clock requirements and performance,? on page 21. ? ?external 32.768 khz low-power oscillator? on page 22. ? table 3: ?external 32.768 khz low-power oscillator specifications,? on page 22. ? table 6: ?gspi registers,? on page 31. ? table 8: ?wlbga signal descriptions,? on page 49. ? table 9: ?bcm43362 during reset and after reset or during sleep,? on page 55. ? table 12: ?environmental ratings,? on page 59. ? table 13: ?esd specifications,? on page 59. ? table 14: ?recommended operating conditions and dc characteristics,? on page 60. ? table 16: ?wlan 2.4 ghz receiver performance specifications,? on page 62. ? table 17: ?wlan 2.4 ghz transmitter performance specifications,? on page 65. ? table 18: ?general spurious emissions specifications,? on page 67. ? table 19: ?core buck regulator,? on page 68. ? table 20: ?3.3v ldo (ldo3p3),? on page 71. ? table 21: ?cldo,? on page 72. ? table 22: ?lnldo1,? on page 73. ? ?gspi signal timing? on page 78. 43362-ds100-r 7/15/10 initial release revision date change description table of contents bcm43362 data sheet broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 4 broadcom confidential table of contents about this document ............................................................................................................................... ... 9 purpose and audience ........................................................................................................... ................. 9 acronyms and abbreviations..................................................................................................... .............. 9 document conventions ........................................................................................................... ................ 9 references ..................................................................................................................... ....................... 10 technical support ............................................................................................................................... ....... 10 section 1: overview .......................................................................................................... 11 overview ............................................................................................................................... ....................... 11 standards compliance ............................................................................................................................... 12 section 2: power supplies and power management ..................................................... 13 wlan power management ........................................................................................................................ 13 power supply topology ............................................................................................................................. 14 voltage regulators ............................................................................................................................... ...... 15 pmu sequencing ............................................................................................................................... ......... 15 low-power shutdown ............................................................................................................................... .16 cbuck regulator features ....................................................................................................................... 16 section 3: frequency references.................................................................................... 18 crystal interface and clock generation ................................................................................................... 18 tcxo ............................................................................................................................... ............................. 19 external 32.768 khz low-power oscillator .............................................................................................. 21 section 4: wlan system interfaces................................................................................ 22 sdio v2.0 ............................................................................................................................... ...................... 22 sdio pin descriptions.......................................................................................................... ................. 22 generic spi mode ............................................................................................................................... ........ 24 spi protocol ................................................................................................................... ....................... 24 command structure .............................................................................................................. ......... 27 write.......................................................................................................................... ..................... 27 write/read ..................................................................................................................... ................ 27 read........................................................................................................................... .................... 27 status ......................................................................................................................... .................... 28 gspi host-device handshake..................................................................................................... .......... 30 boot-up sequence ............................................................................................................... ................. 30 external coexistence interface ................................................................................................................ 33 section 5: wireless lan mac and phy .......................................................................... 34 mac features ............................................................................................................................... .............. 34 mac description ................................................................................................................ ................... 34 table of contents bcm43362 data sheet broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 5 broadcom confidential psm ............................................................................................................................ ................... 35 wep ............................................................................................................................ ................... 36 txe ............................................................................................................................ .................... 36 rxe............................................................................................................................ .................... 36 ifs............................................................................................................................ ...................... 37 tsf ............................................................................................................................ .................... 37 nav............................................................................................................................ .................... 37 mac-phy interface.............................................................................................................. .......... 37 phy description ............................................................................................................................... .......... 38 phy features................................................................................................................... ..................... 38 section 6: wlan radio subsystem ................................................................................ 41 receive path ............................................................................................................................... ................ 42 transmit path ............................................................................................................................... ............... 42 calibration ............................................................................................................................... .................... 42 section 7: cpu and global functions ............................................................................. 43 wlan cpu and memory subsystem ........................................................................................................ 43 one-time programmable memory ............................................................................................................ 43 gpio interface ............................................................................................................................... .............. 44 jtag interface ............................................................................................................................... ............ 44 uart interface ............................................................................................................................... ............ 44 section 8: wlan software architecture ......................................................................... 45 host software architecture ....................................................................................................................... 45 device software architecture .................................................................................................................... 45 remote downloader.............................................................................................................. ................ 46 wireless configuration utility ................................................................................................................... 46 section 9: pinout and signal descriptions ..................................................................... 47 signal assignments ............................................................................................................................... .... 47 wlan gpio signals and strapping options ........................................................................................... 56 section 10: dc characteristics ........................................................................................ 57 absolute maximum ratings ...................................................................................................................... 57 environmental ratings .............................................................................................................................. 5 8 electrostatic discharge specifications .................................................................................................... 58 recommended operating conditions and dc characteristics ............................................................. 59 section 11: wlan rf specifications .............................................................................. 61 2.4 ghz band general rf specifications ................................................................................................. 62 wlan 2.4 ghz receiver performance specifications ............................................................................ 62 wlan 2.4 ghz transmitter performance specifications ....................................................................... 65 table of contents bcm43362 data sheet broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 6 broadcom confidential general spurious emissions specifications ........................................................................................... 67 section 12: internal regulator electrical specifications ............................................... 68 core buck regulator ............................................................................................................................... ... 68 3.3v ldo (ldo3p3) ............................................................................................................................... ..... 71 cldo ............................................................................................................................... ............................ 72 lnldo1 ............................................................................................................................... ........................ 73 section 13: system power consumption........................................................................ 74 section 14: interface timing and ac characteristics .................................................... 75 sdio default mode timing ........................................................................................................................ 75 sdio high-speed mode timing ................................................................................................................. 77 gspi signal timing ............................................................................................................................... ...... 78 jtag timing ............................................................................................................................... ................ 79 section 15: package information ..................................................................................... 80 package thermal characteristics ............................................................................................................. 80 junction temperature estimation and psi versus theta jc ................................................................... 80 section 16: mechanical information ................................................................................ 81 section 17: ordering information .................................................................................... 82 list of figures bcm43362 data sheet broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 7 broadcom confidential list of figures figure 1: bcm43362 system block diagram ......................................................................................... ........... 1 figure 2: bcm43362 block diagram ................................................................................................ ............... 11 figure 3: power topology ........................................................................................................ ........................ 14 figure 4: recommended oscillator configuration .................................................................................. ......... 18 figure 5: recommended circuit to use with an external dedicated tcxo .................................................... 19 figure 6: recommended circuit to use with an external shared tcxo......................................................... 19 figure 7: signal connections to sdio host (sd 4-bit mode) ....................................................................... ... 22 figure 8: signal connections to sdio host (sd 1-bit mode) ....................................................................... ... 23 figure 9: signal connections to sdio host (gspi mode) ........................................................................... .... 24 figure 10: gspi write protocol .................................................................................................. ...................... 25 figure 11: gspi read protocol ................................................................................................... ..................... 26 figure 12: gspi command structure............................................................................................... ................ 27 figure 13: gspi signal timing without status.................................................................................... ............. 28 figure 14: gspi signal timing with status (response delay = 0).................................................................. .29 figure 15: wlan boot-up sequence ................................................................................................ .............. 32 figure 16: 4-wire coexistence wiring ............................................................................................ ................. 33 figure 17: wlan mac architecture ................................................................................................ ................ 35 figure 18: wlan phy block diagram............................................................................................... .............. 39 figure 19: stbc receive block diagram........................................................................................... ............. 40 figure 20: radio functional block diagram ....................................................................................... ............. 41 figure 21: wlan software architecture ........................................................................................... ............... 46 figure 22: 69-ball wlbga ball map............................................................................................... ................. 47 figure 23: rf port location..................................................................................................... ........................ 61 figure 24: cbuck efficiency..................................................................................................... ...................... 70 figure 25: sdio bus timing (default mode) ....................................................................................... ............ 75 figure 26: sdio bus timing (high-speed mode).................................................................................... ........ 77 figure 27: gspi timing .......................................................................................................... .......................... 78 figure 28: 69-ball wlbga mechanical information ................................................................................. ....... 81 list of tables bcm43362 data sheet broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 8 broadcom confidential list of tables table 1: cbuck operating mode selection......................................................................................... ........... 17 table 2: crystal oscillator and external clock requirements and performance............................................. 20 table 3: external 32.768 khz low-power oscillator specifications ................................................................ 21 table 4: sdio pin descriptions .................................................................................................. ..................... 22 table 5: gspi status field details .............................................................................................. ..................... 29 table 6: gspi registers ......................................................................................................... .......................... 30 table 7: coexistence signals .................................................................................................... ...................... 33 table 8: wlbga signal descriptions .............................................................................................. ................ 48 table 9: bcm43362 during reset and after reset or during sleep ............................................................... 54 table 10: gpio functions and strapping options.................................................................................. ......... 56 table 11: absolute maximum ratings .............................................................................................. ............... 57 table 12: environmental ratings ................................................................................................. .................... 58 table 13: esd specifications .................................................................................................... ...................... 58 table 14: recommended operating conditions and dc characteristics ........................................................ 59 table 15: 2.4 ghz band general rf specifications................................................................................ ........ 62 table 16: wlan 2.4 ghz receiver performance specifications .................................................................... 62 table 17: wlan 2.4 ghz transmitter performance specifications ................................................................ 65 table 18: general spurious emissions specifications ............................................................................. ....... 67 table 19: core buck regulator................................................................................................... ..................... 68 table 20: 3.3v ldo (ldo3p3) ..................................................................................................... ................... 71 table 21: cldo .................................................................................................................. ............................. 72 table 22: lnldo1 ................................................................................................................ ........................... 73 table 23: system power consumption.............................................................................................. .............. 74 table 24: sdio bus timing parameters (default mode) ............................................................................ .... 75 table 25: sdio bus timing parameters (high-speed mode) ........................................................................ 7 7 table 26: gspi timing parameters ................................................................................................ .................. 78 table 27: jtag timing characteristics ........................................................................................... ................ 79 table 28: package thermal characteristics ....................................................................................... ............. 80 broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 9 bcm43362 data sheet broadcom confidential about this document purpose and audience this document provides engineering design information for the bcm43362, a single chip with an integrated 2.4 ghz rf transceiver, mac, and baseband processor that fully supports the ieee 802.11? b/g/n standards. the information provided is intended for hardware design engineers who will be incorporating the bcm43362 into their designs. acronyms and abbreviations in most cases, acronyms and abbreviations are defined on first use. for a comprehensive list of acronyms and other terms used in broadcom documents, go to: http://www.broadcom.com/press/glossary.php . document conventions the following conventions may be used in this document: convention description bold user input and actions: for example, type exit , click ok, press alt+c monospace code: #include command line commands and parameters: wl [-l] |
broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 10 bcm43362 data sheet broadcom confidential references the references in this section may be used in conjunction with this document. for broadcom documents, replace the ?xx? in the document number with the largest number available in the repository to ensure that you have the most current version of the document. technical support broadcom provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, pcb layout information, and software updates through its customer support portal ( https://support.broadcom.com ). for a csp account, contact your sales or engineering support representative. in addition, broadcom provides other product support through its downloads & support site ( http://www.broadcom.com/support/ ). note: broadcom provides customer access to technical documentation and software through its customer support portal (csp) and downloads & support site (see technical support ). document (or item) name number source broadcom items [1] bcm43362 reference board schematics ? broadcom representative overview broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 11 bcm43362 data sheet broadcom confidential section 1: overview overview the broadcom? bcm43362 provides the highest level of integration for a mobile or handheld wireless system, with integrated ieee 802.11 b/g/n. it provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. the bcm43362 is designed to address the needs of highly mobile devices that require minimal power consumption and reliable operation. figure 2 shows the interconnect of all the major physical blocks in the bcm43362 and their associated external interfaces, which are described in greater detail in the following sections. figure 2: bcm43362 block diagram backplane ram (240 kb) rom (448 kb) pmu ctrl lpo swreg ldo sleep clk 2.4 ghz pa (int) gpio uart jtag jtag arm processor sdiod gspi mac single-stream 802.11n phy radio 802.11b/g/n gpio uart jtag otp wdog timer bt coex ext lna/rf switch control power supply sdio/spi por wl_rst_n xtal osc dedicated crystal or tcxo always on buffer tcxo signal shared with bt/fm/gps chip standards compliance broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 12 bcm43362 data sheet broadcom confidential standards compliance the bcm43362 supports the following standards: ? ieee 802.11n ? 802.11b ? 802.11g ? 802.11d ? 802.11h ? 802.11i ? 802.11j the bcm43362 will support the following future drafts/standards: ? 802.11w?secure management frames ? 802.11 extensions: ?wmm? ? 802.11i mac enhancements ? 802.11r fast roaming support (between aps) ? 802.11k radio resource measurement ? security: ?wep ?wapi ? wpa? personal ? wpa2? personal ? aes (hardware accelerator) ? tkip (hw accelerator) ? ckip (sw support) ? qos protocols: ?wmm ? wwm-ps (u-apsd) ?wwm-sa ? proprietary protocols: ?wfaec ? coexistence interfaces: ? supports ieee 802.15.2 external three-wire coexistence scheme to support additional wireless technologies, such as bluetooth, zigbee, or bt smart. power supplies and power management broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 13 bcm43362 data sheet broadcom confidential section 2: power supplies and power management wlan power management the bcm43362 has been designed with the stringent power consumption requirements of mobile devices in mind. all areas of the chip design are optimized to minimize power consumption. silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. additionally, the bcm43362 integrated ram is a low-leakage memory with dynamic clock control. the dominant supply current consumed by the ram is leakage current only. additionally, the bcm43362 includes an advanced wlan power management unit (pmu) sequencer. the pmu sequencer provides significant power savings by putting the bcm43362 into various power management states appropriate to the current environment and activities that are being performed. the power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. power-up sequences are fully programmable. configurable, free-running counters, which run on the 32.768 khz low-power oscillator (lpo) sleep clock in the pmu sequencer, are used to turn individual regulators and power switches on and off. clock speeds are dynamically changed, or gated off, as appropriate for the current mode. slower clock speeds are used wherever possible. the bcm43362 power states are described as follows: ? active mode?all components in the bcm43362 are powered up and fully functional with active carrier sensing and frame transmission and receiving. all required regulators are enabled and put in the most efficient mode (pwm or burst) based on the load current. clock speeds are dynamically adjusted by the pmu sequencer. ? sleep mode?the radio, afe, plls, and the crystal oscillator are powered down. the rest of the bcm43362 remains powered up in an idle state. all main clocks are shut down. the 32.768-khz lpo sleep clock is available only for the pmu sequencer. this condition is necessary to allow the pmu sequencer to wake up the chip and transition to active mode. in sleep mode, the primary power consumed is due to leakage current. ? power-down modes?the bcm43362 has a full power-down mode and a low-power shutdown mode. a full power-down occurs when there is no vio voltage, and wl_rst_n and ext_smprs_req are low. a low-power shutdown occurs when vio is present, and wl_rst_n and ext_smprs_req are low. in low- power shutdown, only the band gap and ldo3p3 are on. both power-down modes are exited when the host asserts either wl_rst_n or ext_smps_req high. ? external mode?in this mode, the following are true: ? the assertion of ext_smps_req turns only the core buck (cbuck) regulator on. ? the wlan is in reset (wl_rst_n = low). ? the state of ldo3p3 and the band gap are dependent on vbat and vio. power supply topology broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 14 bcm43362 data sheet broadcom confidential power supply topology the bcm43362 contains a power management unit (pmu), a buck-mode switching regulator, and three low noise ldos. these integrated regulators simplify power supply design in wlan embedded designs. all regulator inputs and outputs are brought out to pins on the bcm43362, providing system designers with the flexibility to choose which of the bcm43362 integrated regulators to use. one option is to supply the pmu from a single, variable power supply, vbat, which can range from 2.3v to 4.8v. using this option, all of the required voltages are provided by bcm43362 regulators except for a low current rail, vio, which must be provided by the host to power the i/o signal buffers when the chip is out of reset. alternately, if specific rails such as 3.3v, 1.8v, and 1.2v already exist in the system, appropriate regulators in the bcm43362 can be bypassed, thereby reducing the cost and board space associated with external regulator components such as inductors and large capacitors. the cbuck and cldo get powered whenever the reset signal is deasserted. the cbuck regulator can be turned on by asserting ext_smps_req high. asserting ext_pwm_req high will set cbuck to pwm mode. driving ext_pwm_req low will put cbuck in burst mode. optionally, lnldo may also be powered. all regulators are powered down only when the reset signal is asserted. figure 3: power topology bcm43362 ln ldo1 section sensitive to power supply noise loads not sensitive to power supply noise cldo vbat 2.3v to 4.8v wl_rst_n 1.4v to 1.8v 1.2v 2.5v to 3.4v 1.2v bcm43362 bcm43362 internal wlan power amplifiers (30 ma) optional (250 ma) external device (bt/fm/gps/other) vio notes: 1 . ldo3p3 is always enabled when vio is present in order to provide bias for vddio_rf and the external rf switch. 2. areas in dark gray are internal to the bcm43362. 3. vddio and vddio_sd can be powered from separate supplies if sdio signaling needs to be at a different level than vddio. this diagram shows the more common case where vddio and vddio_sd are powered from the same supply. ext_pwm_req ext_smps_req vddio_rf wl otp (3.3v) wl radio ? part a rf pll wrf afe wrf xo wrf clpo/ext. lpo wrf lna/rx, bg, rcal wrftx wrf radio ? bb pll wrf otp wl digital, including memory wrf vco and logen vddio internal lnldo ldo3p3 1 core buck regulator vddio_sd voltage regulators broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 15 bcm43362 data sheet broadcom confidential voltage regulators all bcm43362 regulator output voltages are pmu programmable and have the following nominal capabilities. the currents listed below indicate regulator capabilities. see ?system power consumption? on page 74 for the actual expected loads. ? core buck switching regulator (cbuck): 2.3?4.8v input, nominal 1.5v output (up to 500 ma). ? ldo3p3: 2.3?4.8v input, nominal 3.3v output (up to 40 ma) ? cldo (for the core): 1.45?2.0v input, nominal 1.2v output (up to 150 ma) ? low-noise lnldo1: 1.45?2.0v input, nominal 1.2v output (up to 150 ma) see ?internal regulator electrical specifications? on page 68 for full regulator specifications. pmu sequencing the wlan pmu sequencer is responsible for minimizing system power consumption. it enables and disables various system resources based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. resource requests come from several sources: clock requests from cores, the minimum resources defined in the resourcemin register, and the resources requested by any active resource request timers. the pmu sequencer maps clock requests into a set of resources required to produce the requested clocks. each resource is in one of four states: enabled, disabled, transition_on, and transition_off. each resource has a timer that contains 0 when the resource is enabled or disabled and a nonzero value in the transition states. the timer is loaded with the resource's time_on or time_off value when the pmu determines that the resource must be enabled or disabled. that timer decrements on each lpo sleep clock. when it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. if the time_on value is 0, the resource can go immediately from disabled to enabled. similarly, a time_off value of 0 indicates that the resource can go immediately from enabled to disabled. the terms enable sequence and disable sequence refer to either the immediate transition or the timer load-decrement sequence. during each clock cycle, the pmu sequencer performs the following actions: 1. computes the required resource set based on requests and the resource dependency table. 2. decrements all timers whose values are nonzero. if a timer reaches 0, the pmu clears the resourcepending bit for the resource and inverts the resourcestate bit. 3. compares the request with the current resource status and determines which resources must be enabled or disabled. 4. initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered-up dependents. 5. initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled. low-power shutdown broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 16 bcm43362 data sheet broadcom confidential low-power shutdown the bcm43362 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other device in the system, remain operational. when wlan is not needed, the wlan core can be put in reset by asserting wl_rst_n (logic low). vddio_rf and vddio remain powered while vio and vbat are both present, allowing the bcm43362 to be effectively off while keeping the i/o pins powered. during a low- power shut-down state, provided vio continues to be supplied to the bcm43362, most outputs are tristated and most inputs are disabled. input voltages must remain within the limits defined for normal operation. this is done to prevent current paths or create loading on any digital signals in the system, enabling the bcm43362 to be a fully integrated embedded device that takes full advantage of the lowest power-saving modes. two signals on the bcm43362, the system clock input (oscin) and sleep clock input (ext_sleep_clk), are designed to be high-impedance inputs that do not load down the driving signal even if the bcm43362 does not have vddio power applied to it. when the bcm43362 is powered on from this state, it is the same as a normal power-up, and the device does not contain any information about its state from before it was powered down. cbuck regulator features the cbuck regulator has several features that help make the bcm43362 ideal for mobile devices. first, the regulator uses 3.2 mhz as its pwm switching frequency for buck regulation. this high frequency allows the use of small passive components for the switcher's external circuit, thereby saving pcb space in the design. in addition, the cbuck regulator has three modes of operation: pwm mode for low-ripple output and for fast transient response and extended load ranges, burst mode for lower currents, and low power burst mode for higher efficiency when the load current is very low (low power burst mode is not available for external devices). the cbuck supports external smps request to allow flexibility of supplying 1.8v to bcm43362, bcm2076, and other external devices when ext_smps_req is asserted high. it also supports low ripple pwm mode (7 mvpp typical) for noise-sensitive applications when ext_pwm_req is asserted high. a 100 s wait/settling time from the assertion of ext_pwm_req high before increasing the load current allows the internal integrator precharging to complete. this is not a requirement, but is preferred. cbuck regulator features broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 17 bcm43362 data sheet broadcom confidential table 1 lists the mode the cbuck operates in (burst or pwm), based on various external control signals and internal cbuck mode register settings. for detailed cbuck performance specifications, see ?core buck regulator? on page 68 . table 1: cbuck operating mode selection wl_rst_l ext_smps_req ext_pwm_req internal cbuck mode required cbuck mode 00xxoff 010xburst 011xpwm 1 0 x burst burst 10xpwmpwm 110burstburst 110pwmpwm 111xpwm frequency references broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 18 bcm43362 data sheet broadcom confidential section 3: frequency references an external crystal is used for generating all radio frequencies and normal operation clocking. as an alternative, an external frequency reference driven by a temperature-compensated crystal oscillator (tcxo) signal may be used. no software settings are required to differentiate between the two. in addition, a low-power oscillator (lpo) is provided for lower power mode timing. crystal interface and clock generation the bcm43362 can use an external crystal to provide a frequency reference. the recommended configuration for the crystal oscillator, including all external components, is shown in figure 4 . consult the reference schematics for the latest configuration. figure 4: recommended os cillator configuration the bcm43362 uses a fractional-n synthesizer to generate the radio frequencies, clocks, and data/packet timing. this enables it to operate using numerous frequency references. this may either be an external source such as a tcxo or a crystal interfaced directly to the bcm43362. the default frequency reference setting is a 26 mhz crystal or tcxo. the signal requirements and characteristics for the crystal interface are shown in table 2 on page 20 . note: although the fractional-n synthesizer can support many reference frequencies, frequencies other than the default require support to be added in the driver, plus additional extensive system testing. contact broadcom for further details. 12 ? 27 pf 12 ? 27 pf oscout oscin c c r note : resistor value determined by crystal drive level. see reference schematics for details. tcxo broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 19 bcm43362 data sheet broadcom confidential tcxo as an alternative to a crystal, an external precision tcxo can be used as the frequency reference, provided that it meets the phase noise requirements listed in table 2 on page 20 . when the clock is provided by an external tcxo, there are two possible connection methods, as shown in figure 5 and figure 6 : 1. if the tcxo is dedicated to driving the bcm43362, it should be connected to the osc_in pin through an external 1000 pf coupling capacitor, as shown in figure 5 . the internal clock buffer connected to this pin will be turned off when the bcm43362 goes into sleep mode. when the clock buffer turns on and off, there will be a small impedance variation up to 15%. power must be supplied to the wrf_xtal_vdd1p2 pin. 2. an alternative is to dc-couple the tcxo to the wrf_tcxo_in pin, as shown in figure 6 . use this method when the same tcxo is shared with other devices and a change in the input impedance is not acceptable because it may cause a frequency shift that cannot be tolerated by the other device sharing the tcxo. this pin is connected to a clock buffer powered from wrf_tcxo_vdd3p3. if the power supply to this buffer is always on (even in sleep mode), the clock buffer is always on, thereby ensuring a constant input impedance in all states of the device. the maximum current drawn from wrf_tcxo_vdd3p3 is approximately 500 a. figure 5: recommended circuit to use with an external dedicated tcxo figure 6: recommended circuit to use with an external shared tcxo tcxo nc 1000 pf oscin oscout wrf_tcxo_in wrf_tcxo_vdd3p3 tcxo nc wrf_tcxo_in oscout oscin to other devices wrf_tcxo_vdd3p3 connect to a supply (1.7v to 3.3v) that is powered up or down with the external tcxo clock. tcxo broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 20 bcm43362 data sheet broadcom confidential table 2: crystal oscillator and extern al clock requirements and performance parameter conditions/notes crystal external frequency reference min typ max min typ max units frequency ? between 12 mhz and 52 mhz a a. the frequency step size is approximately 80 hz. the bcm43362 does not auto-detect the reference clock frequency; the frequency is specified in the software/nvram file. crystal load capacitance ??12? pf esr ? ? ? 60 ? input impedance (oscin) b b. the internal clock buffer connected to this pin will be turned off when the bcm43362 goes into sleep mode. when the clock buffer turns on and off, there will be a small impedance variation up to 15%. resistive 30k 100k ? ? capacitive ??7.5 pf input impedance (wrf_tcxo_in) resistive 30k 100k ? ? capacitive ??4 pf oscin input voltage ac-coupled analog signal 400 ? 1200 mv p-p oscin input low level dc-coupled digital signal 0?0.2 v oscin input high level dc-coupled digital signal 1.0 ? 1.36 v wrf_tcxo_in input voltage dc-coupled analog signal c c. this input has an internal dc blocking capacitor, so do not include an external dc blocking capacitor. 400 ? tcxo_ vdd d d. the maximum allowable voltage swing for the wrf_tcxo_in input is equal to the wrf_tcx0_vdd3p3 supply voltage range, which is 1.7v to 3.3v. mv p-p frequency tolerance initial + over temperature ? ?20 ? 20 ?20 ? 20 ppm duty cycle 26 mhz clock 40 50 60 % phase noise e, f (ieee 802.11 b/g) e. for a clock reference other than 26 mhz, 20 log10(f/26) db should be added to the limits, where f = the reference clock frequency in mhz. f. if the selected clock has a flat phase-noise response above 100 khz, then it is acceptable to subtract 1 db from all 1 khz, 10 khz, and 100 khz values shown, and ignore the 1 mhz requirement. 26 mhz clock at 1 khz offset ? ? ?119 dbc/hz 26 mhz clock at 10 khz offset ? ? ?129 dbc/hz 26 mhz clock at 100 khz offset ? ? ?134 dbc/hz 26 mhz clock at 1 mhz offset ? ? ?139 dbc/hz phase noise e, f (ieee 802.11n, 2.4 ghz) 26 mhz clock at 1 khz offset ? ? ?124 dbc/hz 26 mhz clock at 10 khz offset ? ? ?134 dbc/hz 26 mhz clock at 100 khz offset ? ? ?139 dbc/hz 26 mhz clock at 1 mhz offset ? ? ?144 dbc/hz external 32.768 khz low-power oscillator broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 21 bcm43362 data sheet broadcom confidential external 32.768 khz low-power oscillator the bcm43362 uses a secondary low-frequency sleep clock for low-power mode timing. either the internal low- precision lpo or an external 32.768 khz precision oscillator is required. the internal lpo frequency range is approximately 33 khz 30% over process, voltage, and temperature, which is adequate for some applications. however, one trade-off caused by this wide lpo tolerance is a small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing beacons. whenever possible, the preferred approach is to use a precision external 32.768 khz clock that meets the requirements listed in ta b le 3 . note: the bcm43362 will auto-detect the lpo clock. if it senses a clock on the ext_sleep_clk pin, it will use that clock. if it doesn't sense a clock, it will use its own internal lpo. ? to use the internal lpo: tie ext_sleep_clk to ground. do not leave this pin floating. ? to use an external lpo: connect the external 32.768 khz clock to ext_sleep_clk. table 3: external 32.768 khz low -power oscillator specifications symbol parameter condition/notes specification units minimum typical maximum fr frequency ? ? 32768 ? hz ? f/fr frequency tolerance at 25c ?30 ? +30 ppm ?20c sdio v2.0 broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 23 bcm43362 data sheet broadcom confidential figure 8: signal connections to sdio host (sd 1-bit mode) sd host bcm43362 cmd clk data irq generic spi mode broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 24 bcm43362 data sheet broadcom confidential generic spi mode in addition to the full sdio mode, the bcm43362 includes the option of using the simplified generic spi (gspi) interface/protocol. characteristics of the gspi mode include: ? supports up to 50 mhz operation ? supports fixed delays for responses and data from device ? supports alignment to host gspi frames (16 or 32 bits) ? supports up to 2 kb frame size per transfer ? supports little-endian and big-endian configurations ? supports configurable active edge for shifting ? supports packet transfer through dma for wlan gspi mode is enabled using the strapping option pins. see table 10 on page 56 for details. figure 9: signal connections to sdio host (gspi mode) spi protocol the spi protocol supports both 16-bit and 32-bit word operation. byte endianess is supported in both modes. figure 10 and figure 11 show the basic write and write/read commands. sd host bcm43362 di sclk do irq cs generic spi mode broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 25 bcm43362 data sheet broadcom confidential figure 10: gspi write protocol generic spi mode broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 26 bcm43362 data sheet broadcom confidential figure 11: gspi read protocol generic spi mode broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 27 bcm43362 data sheet broadcom confidential command structure the gspi command structure is 32 bits. the bit positions and definitions are as shown in figure 12 . figure 12: gspi command structure write the host puts the first bit of the data onto the bus half a clock-cycle before the first active edge following the cs going low. the following bits are clocked out on the falling edge of the gspi clock. the device samples the data on the active edge. write/read the host reads on the rising edge of the clock requiring data from the device to be made available before the first rising clock edge of the clock burst for the data. the last clock edge of the fixed delay word can be used to represent the first bit of the following data word. this allows data to be ready for the first clock edge without relying on asynchronous delays. read the read command always follows a separate write to set up the wlan device for a read. this command differs from the write/read command in the following respects: a) chip selects go high between the command/address and the data and b) the time interval between the command/address is not fixed. 0 10 27 11 packet length - 11bits * address C 17 bits f1 f0 c a function no: 00 C func 0 01 C func 1 10 C func 2 11 C func 3 command : 0 C read 1 C write bcm_spid command structure 28 29 30 31 access : 0 C fixed address 1 C incremental address * 11h0 = 2048 bytes 0 10 27 11 packet length - 11bits * address C 17 bits f1 f0 c a function no: 00 C func 0: all spi specific registers 01 C func 1: registers and meories belonging to other blocks in the chip (64 bytes max) 10 C func 2: dma channel 1. wlan packets up to 2048 bytes. 11 C func 3: dma channel 2 (optional). packets up to 2048 bytes. command : 0 C read 1 C write bcm_spid command structure 28 29 30 31 access : 0 C fixed address 1 C incremental address * 11h0 = 2048 bytes generic spi mode broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 28 bcm43362 data sheet broadcom confidential status the gspi interface supports status notification to the host after a read/write transaction. this status notification provides information about any packet errors, protocol errors, information about available packet in the rx queue, etc. the status information helps in reducing the number of interrupts to the host. the status-reporting feature can be switched off using a register bit, without any timing overhead. the gspi bus timing for read/write transactions with and without status notification are as shown in figure 13 below and figure 14 on page 29 . see table 5 on page 29 for information on status field details. figure 13: gspi signal timing without status c31 c30 c1 c0 d31 d30 d1 d0 command 32 bits write data 16*n bits cs sclk mosi c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits miso cs sclk mosi response delay c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits miso cs sclk mosi response delay d1 c31 c30 c1 c0 d31 d30 d1 d0 command 32 bits write data 16*n bits cs sclk mosi c31 c30 c1 c0 d31 d30 d1 d0 c31 c30 c1 c0 d31 d30 d1 d0 command 32 bits write data 16*n bits cs sclk mosi c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits miso cs sclk mosi response delay c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits miso cs sclk mosi response delay c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits miso cs sclk mosi response delay d1 c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits miso cs sclk mosi response delay d1 write write-read read generic spi mode broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 29 bcm43362 data sheet broadcom confidential figure 14: gspi signal timing with status (response delay = 0) table 5: gspi status field details bit name description 0 data not available the requested read data is not available. 1 underflow fifo underflow occurred due to current (f2, f3) read command. 2 overflow fifo overflow occurred due to current (f1, f2, f3) write command. 3 f2 interrupt f2 channel interrupt 5 f2 rx ready f2 fifo is ready to receive data (fifo empty). 7 reserved ? 8 f2 packet available packet is available/ready in f2 tx fifo. 9:19 f2 packet length length of packet available in f2 fifo c31 c0 d31 d1 d0 read data 16*n bits miso cs sclk mosi s0 s31 status 32 bits c31 c0 d31 d1 d0 command 32 bits read data 16*n bits miso cs sclk mosi s0 s31 status 32 bits c31 s0 c1 c0 d31 s31 d1 d0 command 32 bits write data 16*n bits cs sclk mosi s1 status 32 bits miso c31 c0 d31 d1 d0 s0 s31 c31 c0 d31 d1 d0 s0 s31 c31 c0 d31 d1 d0 s0 s31 c31 c0 d31 d1 d0 s0 s31 c31 s0 c1 c0 d31 s31 d1 d0 s1 c31 s0 c1 c0 d31 s31 d1 d0 s1 command 32 bits write write-read read generic spi mode broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 30 bcm43362 data sheet broadcom confidential gspi host-device handshake to initiate communication through the gspi after power-up, the host needs to bring up the wlan/chip by writing to the wake-up wlan register bit. writing a 1 to this bit will start up the necessary crystals and plls so that the bcm43362 is ready for data transfer. the device can signal an interrupt to the host indicating that the device is awake and ready. this procedure also needs to be followed for waking up the device in sleep mode. the device can interrupt the host using the wlan irq line whenever it has any information to pass to the host. on getting an interrupt, the host needs to read the interrupt and/or status register to determine the cause of interrupt and then take necessary actions. boot-up sequence after power-up, the gspi host needs to wait 50 ms for the device to be out of reset. for this, the host needs to poll with a read command to f0 addr 0x14. address 0x14 contains a predefined bit pattern. as soon as the host gets a response back with the correct register content, it implies that the device has powered up and is out of reset. after that, the host needs to set the wakeup-wlan bit (f0 reg 0x00 bit 7). wakeup-wlan turns the pll on; however, the pll doesn't lock until the host programs the pll registers to set the crystal frequency. for the first time after power-up, the host needs to wait for the availability of low-power clock inside the device. once that is available, the host needs to write to a pmu register to set the crystal frequency. this will turn on the pll. after the pll is locked, the chipactive interrupt is issued to the host. this indicates device awake/ready status. see ta b le 6 for information on gspi registers. in ta b le 6 , the following notation is used for register access: ? r: readable from host and cpu ? w: writable from host ? u: writable from cpu table 6: gspi registers address register bit access default description x0000 word length 0 r/w/u 0 0: 16-bit word length 1: 32-bit word length endianess 1 r/w/u 0 0: little endian 1: big endian high-speed mode 4 r/w/u 1 0: normal mode. sample on spiclk rising edge, output on falling edge. 1: high-speed mode. sample and output on rising edge of spiclk (default). interrupt polarity 5 r/w/u 1 0: interrupt active polarity is low. 1: interrupt active polarity is high (default). wake-up 7 r/w 0 a write of 1 will denote wake-up command from host to device. this will be followed by a f2 interrupt from gspi device to host, indicating device awake status. generic spi mode broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 31 bcm43362 data sheet broadcom confidential figure 15 on page 32 shows the wlan boot-up sequence from power-up to firmware download, including the initial device power-on reset (por) evoked by the wl_rst_n signal. after initial power-up, the wl_rst_n signal can be held low to disable the bcm43362 or pulsed low to induce a subsequent reset. x0002 status enable 0 r/w 1 0: no status sent to host after read/write 1: status sent to host after read/write interrupt with status 1 r/w 0 0: do not interrupt if status is sent 1: interrupt host even if status is sent x0003 reserved ? ? ? ? x0004 interrupt register 0 r/w 0 requested data not available; cleared by writing a 1 to this location 1 r 0 f2/f3 fifo underflow due to last read 2 r 0 f2/f3 fifo overflow due to last write 5 r 0 f2 packet available 6 r 0 f3 packet available 7 r 0 f1 overflow due to last write x0005 interrupt register 5 r 0 f1 interrupt 6 r 0 f2 interrupt 7 r 0 f3 interrupt x0006, x0007 interrupt enable register 15:0 r/w/u 16'he0e7 particular interrupt is enabled if a corresponding bit is set x0008 to x000b status register 31:0 r 32'h0000 same as status bit definitions x000c, x000d f1 info register 0 r 1 f1 enabled 1 r 0 f1 ready for data transfer 13:2 r/u 12'h40 f1 max packet size x000e, x000f f2 info register 0 r/u 1 f2 enabled 1 r 0 f2 ready for data transfer 15:2 r/u 14'h800 f2 max packet size x0014 to x0017 test?read only register 31:0 r 32'hfeedb ead this register contains a predefined pattern, which the host can read and determine if the gspi interface is working properly. x0018 to x001b test?r/w register 31:0 r/w/u 32'h000000 00 this is a dummy register where the host can write some pattern and read it back to determine if the gspi interface is working properly. x001c to x001f response delay registers 7:0 r/w 0x1d = 4, other registers = 0 individual response delays for f0, f1, f2, and f3. the value of the registers is the number of byte delays that are introduced before data is shifted out of the gspi interface during host reads. note: the bcm43362 has an internal power-on reset (por) circuit. the device will be held in reset for a maximum of 3 ms after vdd and vddio have both passed the 0.6v threshold. table 6: gspi registers (cont.) address register bit access default description generic spi mode broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 32 bcm43362 data sheet broadcom confidential figure 15: wlan boot-up sequence < 1.5 ms after 8 ms 1 the reference clock is assumed to be up. access to pll registers is possible. 8 1 ms < 50 ms < 3 ms after a fixed delay following internal por going high, the device responds to host f0 (address 0x14) reads. vddio wl_rst_n/ ext_smps_req vddc (from internal pmu) internal por device requests for reference clock spi host interaction: host polls f0 (address 0x14) until it reads a predefined pattern. host sets wake-up-wlan bit and waits 8 ms 1 , the maximum time for reference clock availability. after 8 1 ms, the host programs the pll registers to set the crystal frequency host downloads code. chip-active interrupt is asserted after the pll locks 32.768 khz lpo sleep clock vbat ramp time from 0v to 4.3v > 40 s 0.6v > 2 sleep clock cycles wl_irq 1 this wait time is programmable in sleep clock increments from 1 to 255 (30 us to 8 ms) external coexistence interface broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 33 bcm43362 data sheet broadcom confidential external coexistence interface to manage wireless medium sharing for optimal performance, an external coexistence interface is provided that enables signaling between the bcm43362 and one or two external collocated wireless devices such as bluetooth and/or wimax. note that three of the external coexistence interface pins are multiplexed with gpios. by default, the pins are bt_coex pins. through software they can be changed to gpios. the fourth bt_coex signal is also multiplexed with a gpio, but this one is a gpio by default and can be changed via software to be btcx_freq. see ?pinout and signal descriptions? on page 47 for more details. the signals in ta b l e 7 can be enabled by software. figure 16: 4-wire coexistence wiring table 7: coexistence signals signal description btcx_status coexistence signal indicating bluetooth priority status and tx/rx direction. btcx_rf_active coexistence signal indicating that bluetooth is active. btcx_freq indicates that the coexisting bluetooth is about to transmit on a restricted channel. btcx_txconf coexistence output giving bluetooth permission to transmit. bcm43362 coexisting device btcx_rf_active btcx_freq btcx_txconf btcx_status rf_active priority 2 txconf status coex_in coex_out_0 coex_out_1 c_gpio_1 * note: the pull-down is only required if the coexisting device has the potential to float the signal. r* r* r* r wireless lan mac and phy broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 34 bcm43362 data sheet broadcom confidential section 5: wireless lan mac and phy mac features the bcm43362 wlan mac supports features specified in the ieee 802.11 base standard, and amended by ieee 802.11n. the salient features are listed below: ? transmission and reception of aggregated mpdus (a-mpdu) ? support for power management schemes, including wmm power-save, power-save multipoll (psmp) and multiphase psmp operation. ? support for immediate ack and block-ack policies ? interframe space timing support, including rifs ? support for rts/cts and cts-to-self frame sequences for protecting frame exchanges ? back-off counters in hardware for supporting multiple priorities as specified in the wmm specification ? timing synchronization function (tsf), network allocation vector (nav) maintenance, and target beacon transmission time (tbtt) generation in hardware ? hardware off-load for aes-ccmp, legacy wpa tkip, legacy wep ciphers, wapi, and support for key management ? support for coexistence with bluetooth and other external radios ? programmable independent basic service set (ibss) or infrastructure basic service set functionality ? statistics counters for mib support mac description the bcm43362 wlan mac is designed to support high throughput operation with low-power consumption. it does so without compromising on bluetooth coexistence policies, thereby enabling optimal performance over both networks. in addition, several power-saving modes that have been implemented allow the mac to consume very little power while maintaining network-wide timing synchronization. the architecture diagram of the mac is shown in figure 17 on page 35 . mac features broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 35 bcm43362 data sheet broadcom confidential figure 17: wlan mac architecture the following sections provide an overview of the important modules in the mac. psm the programmable state machine (psm) is a microcoded engine that provides most of the low-level control to the hardware to implement the ieee 802.11 specification. it is a microcontroller that is highly optimized for flow control operations, which are predominant in implementations of communication protocols. the instruction set and fundamental operations are simple and general, which allows algorithms to be optimized until very late in the design process. it also allows for changes to the algorithms to track evolving ieee 802.11 specifications. the psm fetches instructions from the microcode memory. it uses the shared memory to obtain operands for instructions, as a data store, and to exchange data between both the host and the mac data pipeline (via the shm bus). the psm also uses a scratchpad memory (similar to a register bank) to store frequently accessed and temporary variables. the psm exercises fine-grained control over the hardware engines by programming internal hardware registers (ihr). these ihrs are collocated with the hardware functions they control and are accessed by the psm via the ihr bus. the psm fetches instructions from the microcode memory using an address determined by the program counter, instruction literal, or a program stack. for alu operations, the operands are obtained from shared memory, scratchpad, ihrs, or instruction literals, and the results are written into the shared memory, scratchpad, or ihrs. embedded cpu interface host registers, dma engines tx-fifo 32 kb wep wep, tkip, aes txe tx a-mpdu rxe pmq psm shared memory 6 kb psm ucode memory ext- ihr ifs backoff, btcx tsf nav ihr bus shm bus mac - phy interface rx-fifo 10 kb rx a-mpdu mac features broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 36 bcm43362 data sheet broadcom confidential there are two basic branch instructions: conditional branches and alu based branches. to better support the many decision points in the ieee 802.11 algorithms, branches can depend on either a readily available signals from the hardware modules (branch condition signals are available to the psm without polling the ihrs), or on the results of alu operations. wep the wired equivalent privacy (wep) engine encapsulates all the hardware accelerators to perform the encryption and decryption, as well as mic computation and verification. the accelerators implement the following cipher algorithms: legacy wep, wpa tkip, wpa2 aes-ccmp. based on the frame type and association information, the psm determines the appropriate cipher algorithm to be used. it supplies the keys to the hardware engines from an on-chip key table. the wep interfaces with the txe to encrypt and compute the mic on transmit frames, and the rxe to decrypt and verify the mic on receive frames. wapi is also supported. txe the transmit engine (txe) constitutes the transmit data path of the mac. it coordinates the dma engines to store the transmit frames in the txfifo. it interfaces with wep module to encrypt frames and transfers the frames across the mac-phy interface at the appropriate time determined by the channel access mechanisms. the data received from the dma engines are stored in transmit fifos. the mac supports multiple logical queues to support traffic streams that have different qos priority requirements. the psm uses the channel access information from the ifs module to schedule a queue from which the next frame is transmitted. once the frame is scheduled, the txe hardware transmits the frame based on a precise timing trigger received from the ifs module. the txe module also contains the hardware that allows the rapid assembly of mpdus into an a-mpdu for transmission. the hardware module aggregates the encrypted mpdus by adding appropriate headers and pad delimiters as needed. rxe the receive engine (rxe) constitutes the receive data path of the mac. it interfaces with the dma engine to drain the received frames from the rxfifo. it transfers bytes across the mac-phy interface and interfaces with the wep module to decrypt frames. the decrypted data is stored in the rxfifo. the rxe module contains programmable filters that are programmed by the psm to accept or filter frames based on several criteria such as receiver address, bssid, and certain frame types. the rxe module also contains the hardware required to detect a-mpdus, parse the headers of the containers, and disaggregate them into component mpdus. mac features broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 37 bcm43362 data sheet broadcom confidential ifs the ifs module contains the timers required to determine interframe space timing including rifs timing. it also contains multiple back-off engines required to support prioritized access to the medium as specified by wmm. the interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the phy. these timers provide precise timing to the txe to begin frame transmission. the txe uses this information to send response frames or perform transmit frame-bursting (rifs or sifs separated, as within a txop). the back-off engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or pause the back-off counters. when the back-off counters reach 0, the txe gets notified, so that it may commence frame transmission. in the event of multiple back-off counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies provided by the psm. the ifs module also incorporates hardware that allows the mac to enter a low-power state when operating under the ieee power-saving mode. in this mode, the mac is in a suspended state with its clock turned off. a sleep timer, whose count value is initialized by the psm, runs on a slow clock and determines the duration over which the mac remains in this suspended state. once the timer expires, the mac is restored to its functional state. the psm updates the tsf timer based on the sleep duration, ensuring that the tsf is synchronized to the network. the ifs module also contains the pta hardware that assists the psm in bluetooth coexistence functions. tsf the timing synchronization function (tsf) module maintains the tsf timer of the mac. it also maintains the target beacon transmission time (tbtt). the tsf timer hardware, under the control of the psm, is capable of adopting timestamps received from beacon and probe response frames in order to maintain synchronization with the network. the tsf module also generates trigger signals for events that are specified as offsets from the tsf timer, such as uplink and downlink transmission times used in psmp. nav the network allocation vector (nav) timer module is responsible for maintaining the nav information conveyed through the duration field of mac frames. this ensures that the mac complies with the protection mechanisms specified in the standard. the hardware, under the control of the psm, maintains the nav timer and updates the timer appropriately based on received frames. this timing information is provided to the ifs module, which uses it as a virtual carrier- sense indication. mac-phy interface the mac-phy interface consists of a data path interface to exchange rx/tx data from/to the phy. in addition, there is a programming interface, which can be controlled either by the host or the psm to configure and control the phy. phy description broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 38 bcm43362 data sheet broadcom confidential phy description the bcm43362 wlan digital phy is designed to comply with ieee 802.11b/g/n single stream to provide wireless lan connectivity supporting data rates from 1 mbps to 72 mbps for low-power, high-performance handheld applications. the phy has been designed to meet specification requirements in the presence of interference, radio nonlinearity, and impairments. it incorporates efficient implementations of the filters, fft and viterbi decoder algorithms. efficient algorithms have been designed to achieve maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisition and tracking, channel estimation and tracking. the phy receiver also contains a robust 11b demodulator. the phy carrier sense has been tuned to provide high throughput for ieee 802.11g/11b hybrid networks with bluetooth coexistence. phy features ? supports ieee 802.11b, 11g, 11n single-stream standards. ? supports optional greenfield mode in tx and rx. ? supports optional stbc receive of two space-time stream. ? supports ieee 802.11h/d for worldwide operation. ? algorithms achieving low power, enhanced sensitivity, range, and reliability ? algorithms to maximize throughput performance in presence of bluetooth ? automatic gain control scheme for blocking and non blocking application scenario for cellular applications. ? closed loop transmit power control ? supports per packet rx antenna diversity. ? designed to meet fcc and other regulatory requirements. phy description broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 39 bcm43362 data sheet broadcom confidential figure 18: wlan phy block diagram the phy is capable of fully calibrating the rf front-end to extract the highest performance. on power-up, the phy performs a full calibration suite to correct for iq mismatch and local oscillator leakage. the phy also performs periodic calibration to compensate for any temperature related drift, thus maintaining high- performance over time. a closed loop transmit control algorithm maintains the output power to required level with capability control tx power on a per packet basis. one of the key feature of the phy is two space-time stream receive capability. the stbc scheme can obtain diversity gains by using multiple transmit antennas in ap (access point) in a fading channel environment, without increasing the complexity at the sta. details of the stbc receive are shown in the block diagram in figure 19 on page 40 . filters and radio comp frequency and timing synch carrier sense, agc, and rx fsm radio control block filters and radio comp afe and radio mac interface buffers ofdm demodulate viterbi decoder tx fsm pa comp modulation and coding modulate/ spread frame and scramble fft/ifft cck/dsss demodulate descramble and deframe coex phy description broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 40 bcm43362 data sheet broadcom confidential figure 19: stbc receive block diagram in stbc mode, symbols are processed in pairs. equalized output symbols are linearly combined and decoded. channel estimation is refined on every pair of symbols using the received symbols and reconstructed symbols. equalizer demod combine demapper viterbi channel h symbol memory weighted averaging estimate channel transmitter fft of 2 symbols descramble and deframe h old h upd h new wlan radio subsystem broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 41 bcm43362 data sheet broadcom confidential section 6: wlan radio subsystem the bcm43362 includes an integrated wlan rf transceiver that has been optimized for use in 2.4 ghz wireless lan systems. it is designed to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 ghz unlicensed ism band. the transmit and receive sections include all on-chip filtering, mixing, and gain control functions. improvements to the radio design include shared tx/rx baseband filters and high immunity to supply noise. figure 20: radio functional block diagram shared lpf wl logen wl pll wlan bb voltage regulators lpo/ext lpo/rcal wl adc i wl tx g-mixer wl dac i wl lna1 wl lna2 wl dac q wl adc q wl grx wl gtx wl pa wl pad mux mux i q i q wl rx g-mixer receive path broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 42 bcm43362 data sheet broadcom confidential receive path the bcm43362 has a wide dynamic range, direct conversion receiver. it employs high order on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz ism band. transmit path baseband data is modulated and upconverted to the 2.4 ghz ism band. a linear on-chip power amplifier is included, which is capable of delivering high output powers while meeting ieee 802.11b/g/n specifications without the need for an external pa. this pa can be powered directly from vbat, thereby eliminating the need for a separate paldo. closed-loop output power control is completely integrated. calibration the bcm43362 features dynamic on-chip calibration, eliminating process variation across components. this enables the bcm43362 to be used in high-volume applications, because calibration routines are not required during manufacturing testing. these calibration routines are performed periodically in the course of normal radio operation. examples of this automatic calibration are baseband filter calibration for optimum transmit and receive performance and loft calibration for leakage reduction. in addition, i/q calibration, r calibration, and vco calibration are performed on-chip. cpu and global functions broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 43 bcm43362 data sheet broadcom confidential section 7: cpu and global functions wlan cpu and memory subsystem the bcm43362 includes an integrated arm cortex?-m3 processor with internal ram and rom. the arm cortex-m3 processor is a low-power processor that features low gate count, low interrupt latency, and low-cost debugging. it is intended for deeply embedded applications that require fast interrupt response features. the processor implements the arm? architecture v7-m with support for thumb?-2 instruction set. arm cortex-m3 delivers 30% more performance gain over arm7tdmi. at 0.19 w/mhz, the cortex-m3 is the most power efficient general purpose microprocessor available, outperforming 8- and 16-bit devices on mips/w. it supports integrated sleep modes. arm cortex-m3 uses multiple technologies to reduce cost through improved memory utilization, reduced pin overhead, and reduced silicon area. arm cortex-m3 supports independent buses for code and data access (icode/dcode and system buses). arm cortex-m3 supports extensive debug features including real time trace of program execution. on-chip memory for the cpu includes 240 kb sram and 448 kb rom. one-time programmable memory various hardware configuration parameters may be stored in an internal 1024-bit one-time programmable (otp) memory, which is read by system software after device reset. in addition, customer-specific parameters, including the system vendor id and the mac address, can be stored, depending on the specific board design. the initial state of all bits in an unprogrammed otp device is 0. after any bit is programmed to a 1, it cannot be reprogrammed to 0. the entire otp array can be programmed in a single write cycle using a utility provided with the broadcom wlan manufacturing test tools. alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state can be altered during each programming cycle. prior to otp programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with the reference board design package. documentation on the otp development process is available on the broadcom customer support portal ( http://www.broadcom.com/support) . gpio interface broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 44 bcm43362 data sheet broadcom confidential gpio interface five general purpose i/o (gpio) pins are available on the bcm43362 that can be used to connect to various external devices. gpios are tristated by default. subsequently, they can be programmed to be either input or output pins via the gpio control register. they can also be programmed to have internal pull-up or pull-down resistors. gpio_0 is initially used as a strapping option to select between sdio and spi modes. gpios 3, 4, and 5 are multiplexed with the bluetooth coexistence interface. by default, these pins are bt_coex pins. software can reprogram these pins to behave as gpios. gpio_1 is a gpio by default, but can be reprogrammed by software to become the btcx_freq signal. jtag interface the bcm43362 supports the ieee 1149.1 jtag boundary scan standard for performing device package and pcb assembly testing during manufacturing. in addition, the jtag interface allows broadcom to assist customers by using proprietary debug and characterization test tools during board bring-up. therefore, it is highly recommended to provide access to the jtag pins by means of test points or a header on all pcb designs. uart interface one uart interface can be enabled by software as an alternate function on the jtag pins. uart_rx is available on the jtag_tdi pin, and uart_tx is available on the jtag_tdo pin. the uart is primarily for debugging during development. by adding an external rs-232 transceiver, this uart enables the bcm43362 to operate as rs-232 data termination equipment (dte) for exchanging and managing data with other serial devices. it is compatible with the industry standard 16550 uart, and it provides a fifo size of 64 8 in each direction. wlan software architecture broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 45 bcm43362 data sheet broadcom confidential section 8: wlan software architecture host software architecture the host driver (dhd) provides a transparent connection between the host operating system and the bcm43362 media (for example, wlan) by presenting a network driver interface to the host operating system and communicating with the bcm43362 over an interface-specific bus (spi, sdio, and so on) to: ? forward transmit and receive frames between the host network stack and the bcm43362 device, and ? pass control requests from the host to the bcm43362 device, returning the bcm43362 device responses the driver communicates with the bcm43362 over the bus using a control channel and a data channel to pass control messages and data messages. the actual message format is based on the bdc protocol. device software architecture the wireless device, protocol, and bus drivers are run on the embedded arm? processor using a broadcom- defined operating system called hndrte, which transfers data over a propriety broadcom format over the sdio/spi interface between the host and device (bdc/lmac). the data portion of the format consists of ieee 802.11 frames wrapped in a broadcom encapsulation. the host side architecture provides all missing functionality between a network device and the broadcom device interface. the host can also be customized to provide functionality between the broadcom device interface and a full network device interface. this transfer requires a message-oriented (framed) interconnect between the host and device. the sdio bus is an addressed bus?each host-initiated bus operation contains an explicit device target address?and does not natively support a higher-level data frame concept. broadcom has implemented a hardware/software message encapsulation scheme that ignores the bus operation code address and prefixes each frame with a 4- byte length tag for framing. the device presents a packet-level interface over which data, control, and asynchronous event (from the device) packets are supported. the data and control packets received from the bus are initially processed by the bus driver and then passed on to the protocol driver. if the packets are data packets, they are transferred to the wireless device driver (and out through its medium), and a data packet received from the device medium follows the same path in the reverse direction. if the packets are control packets, the protocol header is decoded by the protocol driver. if the packets are wireless ioctl packets, the ioctl api of the wireless driver is called to configure the wireless device. the microcode running in the d11 core processes all time-critical tasks. wireless configuration utility broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 46 bcm43362 data sheet broadcom confidential remote downloader when the bcm43362 powers up, the dhd initializes and downloads the firmware to run in the device. figure 21: wlan software architecture wireless configuration utility the device driver that supports the broadcom ieee 802.11 family of wireless solutions provides an input/output control (ioctl) interface for making advanced configuration settings. the ioctl interface makes it possible to make settings that are normally not possible when using just the native operating system-specific ieee 802.11 configuration mechanisms. the utility uses ioctls to query or set a number of different driver/chip operating properties. spi/sdio bdc/lmac protocol wireless device driver d11 core dhd host driver pinout and signal descriptions broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 47 broadcom confidential bcm43362 data sheet section 9: pinout and signal descriptions signal assignments figure 22 shows the 69-ball wlbga ball map. table 8 on page 48 shows the wlbga signal descriptions. figure 22: 69-ball wlbga ball map ab c defghjkl 1 wrf_rfin wrf_rfout #n/a wrf_pa_vdd rf_sw_ctrl_0 rf_sw_ctrl_1 vddio_rf vout_3p3 sr_vddbat1 sr_vddbat1 sr_vlx 1 2 #n/a wrf_pa_gnd #n/a wrf_pa_gnd wrf_padrv_gnd rf_sw_ctrl_3 rf_sw_ctrl_2 vdd sr_vddbat2 pmu_avss sr_pvss 2 3 wrf_lna_vdd1p2 #n/a #n/a wrf_padrv_vdd vss vss vss vdd ext_smps_req vout_lnldo1 vdd_ldo 3 4 wrf_lna_gnd wrf_ana_vdd1p2 wrf_gpio_out wrf_ana_gnd gpio_0 vss vss vddio wl_rst_n ext_pwm_req vout_cldo 4 5 wrf_vco_ldo_in_vdd1p8 #n/a wrf_vco_ldo_out_vdd1p2 wrf_res_ext gpio_1 / btcx_freq sdio_data_2 jtag_tdo btcx_txconf/ gpio_3 ext_sleep_clk vddio_sd sdio_data_1 5 6 wrf_vco_gnd #n/a wrf_xtal_gnd oscout wrf_afe_gnd xtal_pu jtag_tms jtag_tdi btcx_status/ gpio_4 sdio_data_3 sdio_data_0 6 7 wrf_tcxo_in wrf_tcxo_vdd3p3 wrf_xtal_vdd1p2 os cin #n/a wrf_afe_vdd1p2 jtag_trst_l jtag_tck btcx_rf_active/ gpio_5 sdio_cmd sdio_clk 7 ab c defghjkl signal assignments broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 48 bcm43362 data sheet broadcom confidential table 8: wlbga signal descriptions ball # signal name type description wlan rf interface a1 wrf_rfin i wlan ieee 802.11n rx input (50 ? ) b1 wrf_rfout o wlan ieee 802.11n internal power amplifier output (50 ? ) d5 wrf_res_ext i connect to external 15 k ? resistor (1%) to ground rf control lines (io supply = vddio_rf) e1 rf_sw_ctrl0 o rf switch control line. default at this pin is high. f1 rf_sw_ctrl1 o rf switch control line. default at this pin is low. g2 rf_sw_ctrl2 o rf switch control line. default at this pin is low. f2 rf_sw_ctrl3 o rf switch control line. default at this pin is low. note: 1. use only rf_sw_ctrl1 and rf_sw_ctrl2 unless diversity is required, in which case rf_sw_ctrl0 and rf_sw_ctrl3 can also be used to select the antenna for a pair of spdt switches. 2. for a transfer switch, use only rf_sw_ctrl1 and rf_sw_ctrl2 with the main antenna to rx when rf_sw_ctrl1 is high. 3. for a diamond-type switch, do the following: ? rf_sw_ctrl0 must select wlan tx, aux antenna. ? rf_sw_ctrl1 must select wlan rx, main antenna. ? rf_sw_ctrl2 must select wlan tx, main antenna. ? rf_sw_ctrl2 must select wlan rx, aux antenna. 4. for cases where a shared antenna is used for wlan and bluetooth, rf_sw_cntrl_0 defaults to high when the bcm43362 is in reset. use a switch topology in which the bluetooth rf path is connected to the antenna when this signal is high. this allows bluetooth access to the antenna when wlan is in reset. 5. the following is a list of the internal pull-up/pull-down resistor strengths for the rf switch control lines when the bcm43362 is in reset: minimum typical maximum ? pup @ 3.3v 39k 58k 69k ? pdn @ 3.3v 39k 58k 67k 6. the default drive strength is 6.0 ma. signal assignments broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 49 bcm43362 data sheet broadcom confidential sdio interface f5 sdio_data_2 i/o sdio data line 2. this pin has an internal weak pull-up resistor. note: by default, the internal pull-up is enabled, but it can be disabled via software. the pull-up resistor is forced on for spi mode since this pin is unused in that mode. l6 sdio_data_0/spi_miso i/o sdio data line 0. this pin has an internal weak pull-up resistor. note: by default, the internal pull-up is enabled, but it can be disabled via software. l5 sdio_data_1/spi_irq i/o sdio data line 1. this pin has an internal weak pull-up resistor. note: by default, the internal pull-up is enabled, but it can be disabled via software. l7 sdio_clk/spi_clk i sdio clock. k6 sdio_data_3/spi_csx i/o sdio data line 3. this pin has an internal weak pull-up resistor. note: by default, the internal pull-up is enabled, but it can be disabled by software. k7 sdio_cmd/spi_mosi i/o sdio command line. this pin has an internal weak pull-up resistor. note: by default, the internal pull-up is enabled, but it can be disabled by software. sdio/spi weak internal pull-up resistances : for 1.8v (minimum, typical, maximum): 34 k ? , 51 k ? , 86 k ? for 2.5v (minimum, typical, maximum): 21 k ? , 32 k ? , 54 k ? for 3.3v (minimum, typical, maximum): 16 k ? , 24 k ? , 37 k ? software programmable sdio/spi drive strength options : for 1.8v: 0.5 ma, 1.0 ma, 1.5 ma, 2.0 ma, 2.5 ma (default), and 3.0 ma for 2.5v: 1.5 ma, 3.0 ma, 4.5 ma, 6.0 ma, 7.5 ma (default), and 9.0 ma for 3.3v: 2.0 ma, 4.0 ma, 6.0 ma, 8.0 ma, 10.0 ma (default), and 12.0 ma jtag interface g6 jtag_tms i for normal operation, connect as described in the jtag specification (ieee std 1149.1). otherwise, if jtag is not used, this pin can be left unconnected (nc) as it has an internal weak pull-up resistor. g5 jtag_tdo o for normal operation, connect as described in the jtag specification (ieee std 1149.1). otherwise, if jtag is not used, this pin can be left unconnected (nc). this pin is also muxed with uart_tx, which can be enabled by software. h6 jtag_tdi i for normal operation, connect as described in the jtag specification (ieee std 1149.1). otherwise, if jtag is not used, this pin can be left unconnected (nc) as it has an internal weak pull-up resistor. this pin is also muxed with uart_rx, which can be enabled by software. h7 jtag_tck i for normal operation, connect as described in the jtag specification (ieee std 1149.1). otherwise, if jtag is not used, this pin can be left unconnected (nc) as it has an internal weak pull-up resistor. table 8: wlbga signal descriptions (cont.) ball # signal name type description signal assignments broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 50 bcm43362 data sheet broadcom confidential g7 jtag_trst_l i for normal operation, connect as described in the jtag specification (ieee std 1149.1). otherwise, if jtag is not used, this pin can be left unconnected (nc) as it has an internal weak pull-up resistor. jtag drive strength: for 1.8v: 1.0 ma for 2.5v: 2.5 ma for 3.3v: 3.0 ma output slewing can be enabled or disabled by software; it is enabled by default. clocks a7 wrf_tcxo_in i reference clock input for use when sharing a tcxo with another chip, such as a bt/fm/gps chip (see ?frequency references? on page 18 ). this input has an internal dc blocking capacitor, so do not include an external dc blocking capacitor. connect directly to the external tcxo. this input pad is powered by the wrf_tcxo_vdd3p3 supply, which should be continually powered whenever the external tcxo is powered, even when the bcm43362 is in reset, thereby ensuring this input maintains a constant load on the tcxo signal in all device modes. if unused, ground this pin. d6 oscout o xtal oscillator amplifier output. see ?frequency references? on page 18 . d7 oscin i xtal oscillator amplifier input. this pin can also be used as the reference clock input from a dedicated (that is, not shared) tcxo. f6 xtal_pu o external reference clock enable (clock_request) default mode (open source) : xtal_pu is driven high when the clock is requested and pulled low with a weak internal pull-down resistor when the clock is not requested. push-pull : always driven high or low (no pu/pd). push-pull mode is enabled by software. xtal_pu internal pull-down (pd) resistances : pd @ 1.8v (minimum, typical, maximum): 356 k ? , 558 k ? , 651 k ? pd @ 2.5v (minimum, typical, maximum): 356 k ? , 559 k ? , 652 k ? pd @ 3.3v (minimum, typical, maximum): 356 k ? , 559 k ? , 653 k ? xtal_pu drive strength : for 1.8v: 2.0 ma for 2.5v: 5.0 ma for 3.3v: 6.0 ma output slewing can be enabled or disabled by software; it is enabled by default. j5 ext_sleep_clk i input pin for optional high-precision 32.768 khz clock (sleep clock). table 8: wlbga signal descriptions (cont.) ball # signal name type description signal assignments broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 51 bcm43362 data sheet broadcom confidential gpio interface e4 gpio_0 i/o this pin is used as a strapping option to select between sdio mode (pull low) or spi mode (pull high). it is strongly recommended to use gpio_0 only as a host bus interface select. this pin has a weak internal pull-down resistor. e5 gpio_1/btcx_freq i/o general-purpose interface pin. this pin is high impedance on power-up and reset. subsequently, it becomes an input or output through software control. this pin has a programmable weak pull-up/down. this gpio can be used as the out-of-band wlan_irq signal for sdio/spi. this pin can also be programmed via software to behave as the btcx_freq coexistence signal. h5 btcx_txconf/gpio_3 ? multiplexed bt_coex/gpio pins. when programmed as gpios, pins are high impedance on power-up and reset. subsequently, they can be individually programmed to become inputs or outputs through software control. they can also be programmed to have internal pull-up or pull-down resistors. only gpio 1, 3, 4, and 5 (total 4) can be used as gpios. gpio drive strength: for 1.8v: 1.0 ma for 2.5v: 2.5 ma for 3.3v: 3.0 ma output slewing can be enabled or disabled by software; it is enabled by default. j6 btcx_status/gpio_4 ? j7 btcx_rf_active/ gpio_5 ? note: the following is a list of the internal pull-up/pull-down resistor strengths for the default strapping options described in the gpio section above: minimum typical maximum ? pup @ 1.8v 40k 59k 70k ? pdn @ 1.8v 39k 58k 67k ? pup @ 2.5v 40k 58k 69k ? pdn @ 2.5v 39k 58k 67k ? pup @ 3.3v 39k 58k 69k ? pdn @ 3.3v 39k 58k 67k miscellaneous signals j4 wl_rst_n i active low wlan reset signal. includes an internal 200 k ? pull- down resistor. within 1.5 ms of wl_rst_n being driven high, the pmu changes this from pd to high-z. software can optionally enable the pull-down resistor. vih = 1.08v to 3.6v. vil < 0.4v. h5 btcx_txconf/gpio_3 o coexistence output giving bluetooth permission to transmit. this pin is muxed and can be changed to a gpio via software. table 8: wlbga signal descriptions (cont.) ball # signal name type description signal assignments broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 52 bcm43362 data sheet broadcom confidential e5 gpio_1/btcx_freq i by default, this pin behaves as a gpio. however, it can be programmed via software to behave as a coexistence signal that indicates that the coexisting bt is about to transmit on a restricted channel. j6 btcx_status/gpio_4 i coexistence signal indicating bluetooth priority status and tx/ rx direction. this pin is muxed and can be changed to a gpio via software. j7 btcx_rf_active/ gpio_5 i coexistence signal indicating that bluetooth is active. this pin is muxed and can be changed to a gpio via software. note: the above bluetooth coexistence and gpio signals have keepers that prevent them from floating when they aren?t connected; however, when they are connected to another component, prevention from floating can?t be assured by the keepers. integrated voltage regulators h1 vout_3p3 o 3.3v low noise ldo output (40 ma) k3 vout_lnldo1 o 1.2v output for low noise ldo1, 150 ma j1, k1 sr_vddbat1 i battery voltage input for cbuck j2 sr_vddbat2 i battery voltage input for band gap and ldop3 j3 ext_smps_req i internal 200 k ? pull-down resistor included. vih = 1.08v to 3.6v, and vil < 0.4v. note: driving this input high sets cbuck to external mode, but it does not power down the rest of the pmu. the pmu powers down when wl_rst_n is low. note: this pin is only used if the bcm43362 switching regulator is also used to power an extern al device. this pin should be connected to ground for applications that do not use this feature. k4 ext_pwm_req i driving this input high forces cbuck into pwm mode. internal 200 k ? pull-down resistor included. vih = 1.08v to 3.6v, and vil < 0.4v. note: this pin is only used if the bcm43362 switching regulator is also used to power an extern al device. this pin should be connected to ground for applications that do not use this feature. l1 sr_vlx o core buck regulator: output to inductor l3 vdd_ldo i input supply pin for cldo and lnldo1 (also acts as the voltage feedback for cbuck). l4 vout_cldo o 1.2v output from the core ldo, 150 ma table 8: wlbga signal descriptions (cont.) ball # signal name type description signal assignments broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 53 bcm43362 data sheet broadcom confidential power supplies b4 wrf_ana_vdd1p2 i 1.2v analog power supply a5 wrf_vco_ldo_in_ vdd1p8 i 1.4v to 1.8v vco/ldo power supply input b7 wrf_tcxo_vdd3p3 i 1.7v to 3.3v supply for the bcm43362 tcxo driver. to maintain a constant load on the tcxo_in pin, even when power is removed from the bcm43362, connect this supply pin to a 1.7v to 3.3v supply that is present whenever the external tcxo is powered up. note that this should be a clean supply (do not use vio). if not used, this pin must be connected to ground. c7 wrf_xtal_vdd1p2 i 1.2v xtal oscillator power supply. this supply is required for all clock options: crystal, dedicated tcxo, and shared tcxo (wrf_tcxo_in). d1 wrf_pa_vdd i internal power amplifier power supply (vbat supported), high current d3 wrf_padrv_vdd i internal power amplifier driver power supply (vbat supported) f7 wrf_afe_vdd1p2 i 1.2v afe power supply h2, h3 vdd i 1.2v digital supply for the core g1 vddio_rf i rf i/o and otp supply (3.3v) h4 vddio i digital i/o supply. k5 vddio_sd i digital i/o supply for sdio interface signals. a3 wrf_lna_vdd1p2 i 1.2v analog supply to the internal lna. c5 wrf_vco_ldo_ out_vdd1p2 o vco ldo output. some designs may require a decoupling capacitor (nominal 0.22 f) for optimal wlan performance. broadcom recommends that a 0201 size footprint for this capacitor be included in all designs in case the capacitor is necessary. ground d4 wrf_ana_gnd ? analog ground a6 wrf_vco_gnd ? vco ground b2, d2 wrf_pa_gnd ? internal power amplifier ground c6 wrf_xtal_gnd ? xtal ground e2 wrf_padrv_gnd ? internal power amplifier driver ground e3, f3, f4, g3, g4 vss ? ground e6 wrf_afe_gnd ? afe ground k2 pmu_avss ? pmu analog ground l2 sr_pvss ? buck regulator: power switch ground a4 wrf_lna_gnd ? internal rx lna ground no connects c4 wrf_gpio_out o no connect table 8: wlbga signal descriptions (cont.) ball # signal name type description signal assignments broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 54 bcm43362 data sheet broadcom confidential table 9: bcm43362 during reset and after reset or during sleep signal name/group i/o type during reset after reset (and after firmware initialization) or during sleep pull r i/o pull r i/o reset/control wl_rst_n digital pd input high z a, b input ext_smps_req digital pd input pd c input ext_pwm_req digital pd input pd c input spi signals spi_sdi digital none high z pu d input spi_sdo digital none high z pu d output spi_clk digital none high z none input spi_cs digital none high z pu d input spi_irq digital none high z pu d output sdio signals sdio_clk digital none high z none input sdio_cmd digital none high z pu d bidirectional sdio_data0 digital none high z pu d bidirectional sdio_data1 digital none high z pu d bidirectional sdio_data2 digital none high z pu d bidirectional sdio_data3 digital none high z pu d bidirectional clock xtal_pu (clk_req) digital pd high z pd e output (high) e, f ext_sleep_clk (external 32.768 khz clock) digital none high z none input oscin (reference clock) clk none high z none input bluetooth coexistence g btcx_txconf digital none high z configurable output btcx_freq digital none high z configurable input btcx_rf_actvive digital none high z configurable input btcx_status digital none high z configurable input signal assignments broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 55 bcm43362 data sheet broadcom confidential rf switch control rf_sw_ctl_0 digital pu high z none output rf_sw_ctl_1 digital pd high z none output rf_sw_ctl_2 digital pd high z none output rf_sw_ctl_3 digital pd high z none output gpios g gpio_x digital none high z configurable configurable a. within 1.5 ms of wl_rst_n being driven high, the pmu changes this from pd to high-z. b. software can optionally enable a weak internal pull-down resistor. c. internal pull-down resistor can be disabled via software. d. software can optionally disable the weak internal pull-up for these signals. e. default mode (open source): xtal_pu is driven high when a clock is requested, and pulled low with a weak internal pull-down resistor when a clock is not requested. push-pull: always driven high or low (no pu/pd). available via a strapping option for the fcfbga and wlcsp packages. f. the clock is not requested during sleep mode. g. the bluetooth coexistence and gpio signals have keepers that prevent them from floating when they aren?t connected; however, when they are connected to another component, prevention from floating can?t be assured by the keepers. table 9: bcm43362 during reset and after reset or during sleep (cont.) signal name/group i/o type during reset after reset (and after firmware initialization) or during sleep pull r i/o pull r i/o wlan gpio signals and strapping options broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 56 bcm43362 data sheet broadcom confidential wlan gpio signals an d strapping options the pins listed in table 10 are sampled at power-on reset (por) to determine the various operating modes. sampling occurs a few milliseconds after an internal por or deassertion of the external por. after the por, each pin assumes the gpio or alternative function specified in the signal descriptions table. each strapping option pin has an internal pull-up (pu) or pull-down (pd) resistor that determines the default mode. to change the mode, connect an external pu resistor to vddio or a pd resistor to gnd, using a 10 k ? resistor or less. note: refer to the reference board schematics for more information. table 10: gpio functions and strapping options pin name wlbga pin # default function description gpio_0 e4 0 spimode_sel this pin selects the host interface mode: ? 0: sdio ?1: gspi dc characteristics broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 57 bcm43362 data sheet broadcom confidential section 10: dc characteristics absolute maximum ratings note: values in this document are design goals and are subject to change based on the results of device characterization. caution! the absolute maximum ratings in ta b le 11 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. functional operation is not guaranteed under these conditions. operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device. table 11: absolute maximum ratings rating symbol value unit dc supply for vbat vbat ?0.5 to 6.0 v dc supply for wlan power amplifier vddpa ?0.5 to 6.0 v dc supply voltage for i/o vddio, vddio_sd ?0.5 to 4.1 v dc supply voltage for rf blocks in chip vddrf ?0.5 to 1.29 v dc supply voltage for core vdd ?0.5 to 1.29 v dc supply voltage for rf i/os vddio_rf ?0.5 to 4.1 v dc input supply voltage for cldo and lnldo ? ?0.5 to 2.1 v wrf_vco_ldo_in_vdd1p8 ? ?0.5 to 2.75 v wrf_tcxo_vdd3p3 ? ?0.5 to 3.63 v wl_rst_n ? ?0.5 to 3.63 v ext_smps_req ? ?0.5 to 3.63 v ext_pwm_req ? ?0.5 to 3.63 v maximum undershoot voltage for i/o v undershoot ?0.5 v maximum overshoot voltage for i/o v overshoot vddio + 0.5 v maximum junction temperature t j 125 c environmental ratings broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 58 bcm43362 data sheet broadcom confidential environmental ratings the environmental ratings are shown in table 12 . electrostatic discharge specifications extreme caution must be exercised to prevent electrostatic discharge (esd) damage. proper use of wrist and heel grounding straps to discharge static electricity is required when handling these devices. always store unused material in its antistatic packaging. table 12: environmental ratings characteristic value units conditions/comments ambient temperature (t a ) ?30 to +85c ? coperation storage temperature ?40 to +125c ? c? relative humidity less than 60 % storage less than 85 % operation table 13: esd specifications pin type symbol condition esd rating unit esd, handling reference: nqy00083, section 3.4, group d9, table b esd_hand_hbm human body model contact discharge per jedec eid/ jesd22-a114 1250 v machine model (mm) esd_hand_mm machine model contact 50 v cdm esd_hand_cdm charged device model contact discharge per jedec eia/ jesd22-c101 175 v recommended operating conditions and dc characteristics broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 59 bcm43362 data sheet broadcom confidential recommended operating conditi ons and dc characteristics functional operation is not guaranteed outside the limits shown in table 14 , and operation outside these limits for extended periods can adversely affect long-term reliability of the device. table 14: recommended operating conditions and dc characteristics element symbol value unit minimum typical maximum dc supply voltage for vbat vbat 2.3 ? 4.8 a a. the maximum continuous supply voltage is 4.8v. brief spikes above this 4.8v can be tolerated. specifically, voltages as high as 5.5v for up to 10 seconds cumulative duration over the lifetime of the device are allowed. voltages as high as 5.0v for up to 250 seconds cumulative duration over the lifetime of the device are allowed. v dc supply for wlan power amplifier vddpa 2.3 3.3 4.8 a v dc supply voltage for core vdd 1.14 1.2 1.26 v dc supply voltage for rf blocks in chip vddrf 1.14 1.2 1.26 v dc supply voltage for i/o vddio, vddio_sd 1.71 ? 3.63 v dc supply voltage for rf i/os vddio_rf 3.13 3.3 3.46 v wrf_vco_ldo_in_vdd1p8 ? 1.4 1.8 1.9 v wrf_tcxo_vdd3p3 (icc = 500 a max) b,c b. the maximum limits for tcxo_vdd3p3 noise are: 20 khz, 100 nv/sqrt(hz); 100 khz, 80 nv/sqrt(hz ); 1 mhz, 50 nv/sqrt(hz); 2 mhz, 30 nv/sqrt (hz) c. conditions for icc = 500 a maximum are: ?30c, 3.3v, 52 mhz. ?1.7 1.83.3v input high voltage (wl_rst_n, ext_smps_req, ext_pwm_req) v ih 1.08 ? 3.6 v input low voltage (wl_rst_n, ext_smps_req, ext_pwm_req) v il ??0.4v input high voltage (vddio = 1.8v) d d. for non-sdio digital i/o only. v ih 1.1 ? vddio v input low voltage (vddio = 1.8v) c v il ? ? 0.7 v input high voltage (vddio = 2.5v) c v ih 1.7 ? vddio v input low voltage (vddio = 2.5v) c v il ? ? 0.8 v input high voltage (vddio = 3.3v) c v ih 2.0 ? vddio v input low voltage (vddio = 3.3v) c v il ? ? 0.8 v sdio input high voltage (vddio_sd = 1.8v) v ih 1.17 ? vddio_sd v sdio input low voltage (vddio_sd = 1.8v) v il ? ? 0.63 v sdio input high voltage (vddio_sd = 2.5v or 3.3v) v ih 2.0 ? vddio_sd v sdio input low voltage (vddio_sd = 2.5v or 3.3v) v il ? ? 0.8 v output low voltage e v ol ? ? 0.4 v output high voltage d v oh vddio ? 0.4v ? ? v input low current i il ? 0.3 ? a input high current i ih ? 0.3 ? a recommended operating conditions and dc characteristics broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 60 bcm43362 data sheet broadcom confidential e. for sdio and non-sdio outputs. wlan rf specifications broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 61 bcm43362 data sheet broadcom confidential section 11: wlan rf specifications the bcm43362 includes an integrated direct conversion radio that supports the 2.4 ghz band. this section describes the rf characteristics of the 2.4 ghz radio. unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in table 12: ?environmental ratings,? on page 58 and table 14: ?recommended operating conditions and dc characteristics,? on page 59 . functional operation outside these limits is not guaranteed. typical values apply for the following conditions: ? vbat = 3.6v ? ambient temperature +25c figure 23: rf port location note: values in this document are design goals and may change based on device characterization results. note: all specifications are measured at the rf port unless otherwise specified. filter bcm43362 t/r rf switch (0.5 db insertion loss) antenna port rf port wlan tx wlan rx chip port 2.4 ghz band general rf specifications broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 62 bcm43362 data sheet broadcom confidential 2.4 ghz band general rf specifications wlan 2.4 ghz receiver perf ormance specifications table 15: 2.4 ghz band general rf specifications item condition minimum typical maximum unit tx/rx switch time including tx ramp down ? ? s rx/tx switch time including tx ramp up ? ? s note: the specifications in ta b le 1 6 are measured at the rf port. table 16: wlan 2.4 ghz receiver performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz operating temperature ? ?30 25 85 c rx sensitivity (8% per for 1024 octet psdu) at wlan rf port a 1 mbps dsss ?95 ?97 ? dbm 2 mbps dsss ?92.5 ?94.5 ? dbm 5.5 mbps dsss ?90 ?92 ? dbm 11 mbps dsss ?87 ?89 ? dbm rx sensitivity (10% per for 1000 octet psdu) at wlan rf port a 6 mbps ofdm ?88 ?90 ? dbm 9 mbps ofdm ?88 ?90 ? dbm 12 mbps ofdm ?86 ?88 ? dbm 18 mbps ofdm ?84 ?86 ? dbm 24 mbps ofdm ?82 ?84 ? dbm 36 mbps ofdm ?79 ?81 ? dbm 48 mbps ofdm ?75 ?77 ? dbm 54 mbps ofdm ?73 ?75 ? dbm rx sensitivity (10% per for 4096 octet psdu) at wlan rf port a . defined for default parameters: gf, 800 ns gi, and non-stbc. 20 mhz channel spacing for all mcs rates mcs7 ?70 ?72 ? dbm mcs6 ?72.5 ?74.5 ? dbm mcs5 ?74.5 ?76.5 ? dbm mcs4 ?78.5 ?80.5 ? dbm mcs3 ?82 ?84 ? dbm mcs2 ?84.5 ?86.5 ? dbm mcs1 ?86.5 ?88.5 ? dbm mcs0 ?88 ?90 ? dbm wlan 2.4 ghz receiver performance specifications broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 63 bcm43362 data sheet broadcom confidential blocking level @ wlan rf port for 1db rx sensitivity degradation (without external filtering). b 698?716 mhz wcdma, lte ?28 ? ? dbm 776?787 mhz wcdma, lte ?28 ? ? dbm 824?849 mhz gsm850 ?19 c ?? dbm 824?849 mhz wcdma, lte ?28 d ?? dbm 880?915 mhz gsm900 ?19 ? ? dbm 880?915 mhz wcdma, lte ?28 ? ? dbm 1710?1785 mhz gsm1800 ?22 ? ? dbm 1710?1785 mhz wcdma, lte ?28 ? ? dbm 1850?1910 mhz gsm1900 ?22 ? ? dbm 1850?1910 mhz wcdma, lte ?28 ? ? dbm 1880?1920 mhz td?scdma ?33 ? ? dbm 1900?1920 mhz lte ?28 ? ? dbm 1910?1930 mhz lte ?28 ? ? dbm 1920?1980 mhz wcdma, lte ?28 ? ? dbm 1930?1990 mhz lte ?32 ? ? dbm 2010?2025 mhz td?scdma ?31 ? ? dbm 2500?2570 mhz wcdma, lte ?50 ? ? dbm 2570?2620 mhz lte ?50 ? ? dbm 3168?4752 mhz uwb ?28 ? ? dbm 3402?3620 mhz wimax ?23 ? ? dbm 6336?8976 mhz uwb ?21 ? ? dbm maximum receive level @ 2.4 ghz @ 1, 2 mbps (8% per, 1024 octets) ?3.5 ? ? dbm @ 5.5, 11 mbps (8% per, 1024 octets) ?9.5 ? ? dbm @ 6?54 mbps (10% per, 1000 octets) ?13 ? ? dbm lpf 3-db bandwidth ? ? 9 ? 10 mhz adjacent channel rejection-dsss (difference between interfering and desired signal [25 mhz apart] at 8% per for 1024 octet psdu with desired signal level as specified in condition/notes) 11 mbps dsss ?70 dbm 35 ? ? db table 16: wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit wlan 2.4 ghz receiver performance specifications broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 64 bcm43362 data sheet broadcom confidential adjacent channel rejection-ofdm (difference between interfering and desired signal (25 mhz apart) at 10% per for 1000 e octet psdu with desired signal level as specified in condition/notes) 6 mbps ofdm ?79 dbm 16 ? ? db 9 mbps ofdm ?78 dbm 15 ? ? db 12 mbps ofdm ?76 dbm 13 ? ? db 18 mbps ofdm ?74 dbm 11 ? ? db 24 mbps ofdm ?71 dbm 8 ? ? db 36 mbps ofdm ?67 dbm 4 ? ? db 48 mbps ofdm ?63 dbm 0 ? ? db 54 mbps ofdm ?62 dbm ?1 ? ? db 65 mbps ofdm ?61 dbm ?2 ? ? db maximum receiver gain ? ? ? 90 ? db gain control step ? ? ? 3 ? db rcpi accuracy f range ?98 dbm to ?75 dbm ?3 ? 3 db range above ?75 dbm ?5 ? 5 db return loss zo = 50 across the dynamic range. 10 ? ? db a. derate by 1.5 db for ?30 c to ?10c and 55c to 85c. b. the cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band for the purpose of this test. it is not intended to indicate any specific usage of each band in any specific country. c. min value is ?23 db for chan 11. d. min value is ?36 dbm for chan 11. e. for 65 mbps, the size is 4096. f. the minimum and maximum values shown have a 95% confidence level. table 16: wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit wlan 2.4 ghz transmitter performance specifications broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 65 bcm43362 data sheet broadcom confidential wlan 2.4 ghz transmitter performance specifications note: the specifications in ta b le 1 7 are measured at the rf port output. table 17: wlan 2.4 ghz transmitter performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz transmitted power in cellular and fm bands at rf port (at 18.5 dbm, 90% duty cycle, 1 mbps cck). a 76?108 mhz fm rx ? ?161 ?159 dbm/hz 170?240 mhz dab ? ?161 ?159 dbm/hz 470?862 mhz dvb-h ? ?161 ?159 dbm/hz 728?746 mhz wcdma, lte ? ?161 ?159 dbm/hz 746?757 mhz wcdma, lte ? ?161 ?159 dbm/hz 869?894 mhz wcdma, lte ? ?161 ?159 dbm/hz 925?960 mhz gsm, wcdma, lte ? ?161 ?159 dbm/hz 1570?1580 mhz gps ? ?155 ?153 dbm/hz 1592?1610 mhz glonass ? ?155 ?153 dbm/hz 1805?1880 mhz gsm, wcdma, lte ? ?155 ?153 dbm/hz 1880?1920 mhz td-scdma ? ?134 ?132 dbm/hz 1850?1910 mhz wcdma, lte ? ?134 ?132 dbm/hz 1910?1930 mhz wcdma, lte ? ?134 ?132 dbm/hz 1900?1920 mhz wcdma, lte ? ?134 ?132 dbm/hz 1930?1990 mhz gsm, wcdma, lte ? ?134 ?132 dbm/hz 2010?2075 mhz td-scdma ? ?125.3 ?123.3 dbm/hz 2110?2170 mhz wcdma, lte ? ?125.3 ?123.3 dbm/hz harmonic level at rf port (at 18 dbm with 90% duty cycle, 1 mbps cck) 4.8?5.0 ghz 2nd harmonic ? ?19.5 ?12.8 dbm/ mhz 7.2?7.5 ghz 3rd harmonic ? ?37.7 ?26.7 dbm/ mhz tx power at rf port for highest power level setting at 25c, vbat = 3.6v and spectral mask and evm compliance b, c evm does not exceed ieee 802.11b (dsss/cck) ?9 db 18.5 ? ? dbm ofdm, bpsk ?8 db 18 ? ? dbm ofdm, qpsk ?13 db 18 ? ? dbm ofdm, 16-qam ?19 db 18 ? ? dbm ofdm, 64-qam (r = 3/4) ?25 db 15.5 ? ? dbm ofdm, 64-qam (r = 5/6) ?28 db 14.5 ? ? dbm wlan 2.4 ghz transmitter performance specifications broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 66 bcm43362 data sheet broadcom confidential tx power control dynamic range ?9??db closed loop tx power variation at highest power level setting (at rf port) across full temperature and voltage range. applies across 5 to 21 dbm output power range. ??1.5db carrier suppression ? 15 ? ? dbc gain control step ? ? 0.25 ? db return loss zo = 50 4 6 ? db load pull variation for output power, evm, and adjacent channel power ratio (acpr) vswr = 2:1. evm degradation ? 3.5 ? db output power variation ?2?db acpr-compliant power level ?15 ?dbm vswr = 3:1. evm degradation ? 4 ? db output power variation ?3?db acpr-compliant power level ?15 ?dbm a. the cellular standards listed indicate only typical usages of that band in some countries. other standards may also be used within those bands. b. derate by 1.5 db for temperatures less than ?10c or mo re than 55c, or voltages less than 3.0v. derate by 3.0 db for voltages of less than 2.7v or voltages of le ss than 3.0v at temperatures less than ?10c or greater than 55c. c. tx power for ch 1 and ch 11 is specified separately by nonvolatile memory parameters to ensure band-edge compliance. table 17: wlan 2.4 ghz transmitter performance specifications (cont.) parameter condition/notes minimum typical maximum unit general spurious emissions specifications broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 67 bcm43362 data sheet broadcom confidential general spurious emissions specifications table 18: general spurious emissions specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz general spurious emissions tx emissions 30 mhz < f < 1 ghz rbw = 100 khz ? ?99 ?96 dbm 1 ghz < f < 12.75 ghz rbw = 1 mhz ? ?44 ?41 dbm 1.8 ghz < f < 1.9 ghz rbw = 1 mhz ? ?68 ?65 dbm 5.15 ghz < f < 5.3 ghz rbw = 1 mhz ? ?88 ?85 dbm rx/standby emissions 30 mhz < f < 1 ghz rbw = 100 khz ? ?99 ?96 dbm 1 ghz < f < 12.75 ghz rbw = 1 mhz ? ?54 ?51 dbm 1.8 ghz < f < 1.9 ghz rbw = 1 mhz ? ?88 ?85 dbm 5.15 ghz < f < 5.3 ghz rbw = 1 mhz ? ?88 ?85 dbm note: the specifications in this table are at the rf port. internal regulator electrical specifications broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 68 bcm43362 data sheet broadcom confidential section 12: internal regulator electrical specifications functional operation is not guaranteed outside the specification limits provided in this section. core buck regulator the specifications for the core buck regulator (cbuck) are provided in ta b l e 1 9 . note: values in this document are design goals and are subject to change based on the results of device characterization. table 19: core buck regulator specification notes minimum typical maximum units input supply voltage ? 2.3 ? 4.8 a volts pwm mode switching frequency ?2.563.23.84mhz pwm output current ? ? ? 500 ma output current limit ? ? 700 ? ma output voltage range programmable, 33.33 mv steps default = 1.8v 1.2 ? 1.833 volts output voltage dc accuracy includes load and line regulation. vbat = 2.7v to 4.8v, load 0 to 500 ma, inductor dcr < 137.5 m ? ?5 ? 5 % pwm ripple voltage, static b measure with 20 mhz bw limit. fixed load (0 to 500 ma). max ripple based on vbat < 4.3v, vout = 1.833v, fs = 3.2 mhz, 1.5 h inductor l > 0.6144 h, cap+board total-esr < 10 m ? , cout > 1.9 f ?720mvpp pwm load step transient voltage error vbat = 2.7v to 4.8v, current step = 150 to 400 ma, 1 sec rise-time based on 0402, 6.3v, x5r, and 4.7 f c ceramic capacitor. ? 100 200 mv pwm line step transient voltage error vbat step from 2.3 to 2.7v, 10 sec rise-time, fixed 500 ma load based on 0402, 6.3v, x5r, and 4.7 f b ceramic capacitor. ?50100mv pwm load regulation a vbat = 2.7v to 4.8v, 10 ma to 500 ma load. inductor dcr < 137.5 m ? ??+ 30 mv core buck regulator broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 69 bcm43362 data sheet broadcom confidential pwm line regulation a vbat = 2.7v to 4.8v, 500 ma load. inductor dcr < 137.5 m ? ??+ 10 mv burst mode ripple voltage, static load < 30 ma. measure with 20 mhz bw limit. ??80mvpp 30 ma < load < 200 ma. measure with 20 mhz bw limit. ??200mvpp burst mode load step transient voltage error vbat = 2.7v to 4.8v, current step 10 to 200 ma, 1 sec rise-time based on 0402, 6.3v, x5r, and 4.7 f b ceramic capacitor. ?60120mv burst mode line step transient voltage error vbat step from 2.3v to 2.7v, 10 sec rise-time, fixed 200 ma load based on 0402, 6.3v, x5r, and 4.7 f b ceramic capacitor. ?50100mv burst mode load regulation vbat = 2.7v to 4.8v, 10 ma to 200 ma load ?3550mv burst line regulation input voltage 2.7 to 4.8v, 200 ma load ? 44 70 mv peak pwm mode efficiency d 200 ma load current 30 ma load current 80 60 90 ? % % burst mode efficiency 5 ma load current 70 80 ? % start-up time from power down ? ? 1350 1500 s burst to pwm mode transient voltage error ensure load current < 200 ma during a mode change ??160mv external inductor see preferred inductor list ? 1.5 ? h external output capacitor ceramic, x5r, 0402, cap-esr < 4 m ? esl < 700 ph at 3.2 mhz, 20%, 6.3v ?4.7? f external input capacitor for sr_vddbat1 pins, ceramic, x5r, 0603, cap-esr < 4 m ? at 3.2 mhz, 10%, 6.3v ?4.7? f input supply voltage ramp-up time 0 to 4.3v 40 ? ? s a. the maximum continuous supply voltage is 4.8v. brief spikes above this 4.8v can be tolerated. specifically, voltages as high as 5.5v for up to 10 seconds cumulative duration over the lifetime of the device are allowed. voltages as high as 5.0v for up to 250 seconds cumulative duration over the lifetime of the device are allowed. b. these are not load or line step transient tests. c. more capacitance can be used to reduce the transient error at the output. d. vbat < 4.3v. inductor dcr < 137.5 m ? , acr < 1 ? . table 19: core buck regulator (cont.) specification notes minimum typical maximum units core buck regulator broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 70 bcm43362 data sheet broadcom confidential an efficiency plot for the cbuck regulator is shown in figure 24 . the plot shows typical performance for nominal process silicon, vout = 1.8v, vbat = 3.6v, and temperature = 25c. figure 24: cbuck efficiency 0 10 20 30 40 50 60 70 80 90 100 0 0 0 1 0 0 1 0 1 1 1 . 0 load in ma power efficiency in % pwm mode burst mode 3.3v ldo (ldo3p3) broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 71 bcm43362 data sheet broadcom confidential 3.3v ldo (ldo3p3) table 20: 3.3v ldo (ldo3p3) specification notes minimum typical maximum units input supply voltage ? 2.3 3.6 4.8 a a. the maximum continuous supply voltage is 4.8v. brief spikes above this 4.8v can be tolerated. specifically, voltages as high as 5.5v for up to 10 seconds cumulative duration over the lifetime of the device are allowed. voltages as high as 5.0v for up to 250 seconds cumulative duration over the lifetime of the device are allowed. volts output current ? ? ? 40 ma output voltage, vo step size 100 mv. default = 3.3v. 2.4 3.3 3.4 volts dropout voltage at max load ? ? 200 mv output voltage dc accuracy include line/load regulation. ?5 ? +5 % quiescent current no load ? 8 17 a line regulation vin from (vo + 0.2v) to 4.8v, maximum load ?0.2 ? +0.2 %vo/v load regulation load from 1 ma to 40 ma ? 0.02 0.05 %vo/ ma leakage current power-down mode ? ? 5 a psrr vbat ?? 3.6v, vo = 2.5v, co = 1 f, max load, 100 hz to 1 mhz 20 ? ? db start-up time from the rising edge of vio as the chip powers up from a full power down (that is, band gap off) ? 1200 1400 s ldo turn-on time ldo turn-on time when rest of chip is up ? ? 100 s in-rush current during turn-on from its output capacitor in fully discharged state ? ? 135 ma external output capacitor, co ceramic, x5r, 0402, (esr: 30 m ? ?200 m ? ), 10%, 10v ?1?f external input capacitor for sr_vddbat2 pin (shared with band gap) ceramic, x5r, 0603, (esr: 30 m ? ?200 m ? ), 10%, 10v ?1?f cldo broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 72 bcm43362 data sheet broadcom confidential cldo table 21: cldo specification notes minimum typical maximum units input supply voltage, vin min = 1.25 + 0.2v = 1.45v. dropout voltage requirement must be met under max load. 1.45 1.5 2.0 volts output current ? ? ? 150 ma output voltage, vo programmable in 25 mv steps 1.075 1.2 1.325 volts dropout voltage at max load ? ? 200 mv output voltage dc accuracy include line/load regulation vin > vo + 0.2v ?4 ? +4 % quiescent current no-load ? 10 15 a line regulation vin from (vo + 0.2v) to 2v, max load ?0.2 ? +0.2 %vo/v load regulation load from 1 ma to 150 ma ? 0.02 0.05 %vo/ ma leakage current power-down ? ? 10 a psrr @1 khz, vin ?? 1.5v, co = 1?2.2 f 20 40 ? db start-up time from full-chip power down a a. with cbuck soft-starting concurrently. ? 1250 1400 s ldo turn-on time ldo turn-on time when rest of chip is up ??180s in-rush current during turn-on from its output capacitor in fully discharged state ??150ma external output capacitor, co (nominal values) ceramic, x5r, 0402, (esr: 30 m ? ?200 m ? ), 10%, 10v ?2.2? f external input capacitor (nominal values) only use an external input cap at vdd_ldo pin if it is not supplied from cbuck output. ceramic, x5r, 0402, (esr: 30 m ? ?200 m ? ), 10%, 10v ?12.2f lnldo1 broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 73 bcm43362 data sheet broadcom confidential lnldo1 table 22: lnldo1 specification notes minimum typical maximum units input supply voltage, vin min = 1.25 + 0.2v = 1.45v dropout voltage requirement must be met under max load. 1.45 1.5 2.0 volts output current ? ? ? 150 ma output voltage, vo programmable in 25 mv steps 1.075 1.2 1.325 volts dropout voltage at max load ? ? 200 mv output voltage dc accuracy include line/load regulation vin > vo+0.2v ?4 ? +4 % quiescent current no-load ? 31 44 a line regulation vin from (vo+0.2v) to 2v, max load ?0.2 ? +0.2 %vo/v load regulation load from 1 ma to 150 ma ? 0.02 0.05 %vo/ma leakage current power-down ? ? 10 a output noise @30 khz, 60 ma load co = 2.2 f @100 khz, 60 ma load co = 2.2 f ??60 30 nv/rt hz nv/rt hz psrr @1 khz, vin ?? 1.5v, co = 2.2 f 20 50 ? db ldo turn-on time ldo turn-on time when rest of chip is up ??180s in-rush current during turn-on from its output capacitor in fully discharged state ??150ma external output capacitor, co (nominal values) ceramic, x5r, 0402, (esr: 30 m ? ?200 m ? ), 10%, 10v ?2.2?f note: recommended inductor for cbuck: 1.5 h 20%. murata? lqm21pn1r5mc0 2.0 1.25 0.55 mm dcr = 0.26 ? 25%. murata lqm2mpn1r5ng0 2.0 1.60 1.00 mm dcr = 0.11 ? 25%. system power consumption broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 74 bcm43362 data sheet broadcom confidential section 13: system power consumption power consumption referenced to vbat @ 3.6v, 20c, vddio = 1.8v, cbuck out = 1.5v. note: ta b l e 2 3 shows typical values. table 23: system power consumption wlan operational modes total (ivbat) off 1 11 a off 2 40 a idle 185 a sleep 5 200 a rx (listen) 3 52 ma rx (active) 4 59 ma power save 6, 9 1.9 ma tx cck (11 mbps at 18.5 dbm) 7, 11 320 ma tx ofdm (54 mbps at 15.5 dbm) 8, 11 270 ma tx ofdm (65 mbps at 14.5 dbm) 10, 11 260 ma note 1: wl_rst_n = low, vddio is not present note 2: wl_rst_n = low, vddio is present note 3: carrier sense (cca) when no carrier present note 4: carrier sense (cs) detect/packet rx note 5: intra-beacon sleep note 6: beacon interval = 102.4 ms, dtim = 1, beacon duration = 1 ms @1 mbps. integrated sleep + wakeup + beacon rx current over 1 dtim interval. note 7: cck power at chip port. duty cycle is 100%. includes pa contribution at 3.6v. note 8: ofdm power at chip port. duty cycle is 100%. includes pa contribution at 3.6v. note 9: in wlan power-saving mode, the following blocks are powered down: crystal oscillator, baseband pll, afe, rf pll, radio note 10: ofdm power at chip port is 16 dbm, duty cycle is 100%, includes pa contribution at 3.6v. the above blocks are turned on in the required order with sufficient time for them to settle. this sequencing is done by the pmu controller that controls the settling time for each of the blocks. it also has information to determine the order in which the blocks should be turned on. the settling times and the dependency order are programmable in the pmu controller. the default clk settling time is set to 8 ms at power-up. it can be reduced after power-up. note 11: absolute junction temperature limits maintained through active thermal monitoring and dynamic tx duty cycle limiting. interface timing and ac characteristics broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 75 bcm43362 data sheet broadcom confidential section 14: interface timing and ac characteristics unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in table 12 on page 58 and table 14 on page 59 . functional operation outside of these limits is not guaranteed. sdio default mode timing sdio default mode timing is shown by the combination of figure 25 and table 24 on page 75 . figure 25: sdio bus timing (default mode) note: values in this document are design goals and are subject to change based on the results of device characterization. table 24: sdio bus timing a parameters (default mode) parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) t wl t wh f pp t thl t isu t tlh t ih t odly (max) t odly (min) input output sdio_clk sdio default mode timing broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 76 bcm43362 data sheet broadcom confidential frequency?data transfer mode fpp 0 ? 25 mhz frequency?identification mode fod 0 ? 400 khz clock low time twl 10 ? ? ns clock high time twh 10 ? ? ns clock rise time ttlh ? ? 10 ns clock fall time tthl ? ? 10 ns inputs: cmd, dat (referenced to clk) input setup time tisu5??ns input hold time tih5??ns outputs: cmd, dat (referenced to clk) output delay time?data transfer mode todly 0 ? 14 ns output delay time?identification mode todly 0 ? 50 ns a. timing is based on cl ? 40 pf load on cmd and data. b. min(vih) = 0.7 vddio and max(vil) = 0.2 vddio. table 24: sdio bus timing a parameters (default mode) parameter symbol minimum typical maximum unit sdio high-speed mode timing broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 77 bcm43362 data sheet broadcom confidential sdio high-speed mode timing sdio high-speed mode timing is shown by the combination of figure 26 and ta b l e 2 5 . figure 26: sdio bus timing (high-speed mode) table 25: sdio bus timing a parameters (high-speed mode) a. timing is based on cl ? 40pf load on cmd and data. parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) b. min(vih) = 0.7 vddio and max(vil) = 0.2 vddio. frequency ? data transfer mode fpp 0 ? 50 mhz frequency ? identification mode fod 0 ? 400 khz clock low time twl7??ns clock high time twh7??ns clock rise time ttlh??3ns clock fall time tthl??3ns inputs: cmd, dat (referenced to clk) input setup time tisu6??ns input hold time tih2??ns outputs: cmd, dat (referenced to clk) output delay time ? data transfer mode todly ? ? 14 ns output hold time toh 2.5 ? ? ns total system capacitance (each line) cl ? ? 40 pf t wl t wh f pp t thl t isu t tlh t ih t odly input output 50% vdd t oh sdio_clk gspi signal timing broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 78 bcm43362 data sheet broadcom confidential gspi signal timing the gspi device always samples data on the rising edge of the clock. figure 27: gspi timing table 26: gspi timing parameters parameter symbol minimum maximum units note clock period t1 20.8 ? ns f max = 48 mhz clock high/low t2/t3 (0.45 t1) ? t4 (0.55 t1) ? t4 ns ? clock rise/fall time t4/t5 ? 2.5 ns ? input setup time t6 5.0 ? ns setup time, simo valid to spi_clk active edge input hold time t7 5.0 ? ns hold time, spi_clk active edge to simo invalid output setup time t8 5.0 ? ns setup time, somi valid before spi_clk rising output hold time t9 5.0 ? ns hold time, spi_clk active edge to somi invalid csx to clock a a. spi_csx remains active for entire duration of gspi read/write/write_read transaction (i.e., overall words for multiple word transaction) ? 7.86 ? ns csx fall to 1st rising edge clock to csx c ? ? ? ns last falling edge to csx high jtag timing broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 79 bcm43362 data sheet broadcom confidential jtag timing table 27: jtag timing characteristics signal name period output maximum output minimum setup hold tck 125 ns ? ? ? ? tdi ? ? ? 20 ns 0 ns tms ? ? ? 20 ns 0 ns tdo ? 100 ns 0 ns ? ? jtag_trst 250 ns ? ? ? ? package information broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 80 bcm43362 data sheet broadcom confidential section 15: package information package thermal characteristics junction temperature estimation and psi versus theta jc package thermal characterization parameter psi-jt ( ? jt ) yields a better estimation of actual junction temperature (t j ) versus using the junction-to-case thermal resistance parameter theta-j c ( ? jc ). the reason for this is ? jc assumes that all the power is dissipated through the top surface of the package case. in actual applications, some of the power is dissipated through the bottom and sides of the package. ? jt takes into account power dissipated through the top, bottom, and sides of the package. the equation for calculating the device junction temperature is as follows: t j = t t + p ?? jt where: ?t j = junction temperature at steady-state condition, c ?t t = package case top center temperature at steady-state condition, c ? p = device power dissipation, watts ? ? jt = package thermal characteristics (no airflow), c/w table 28: package thermal characteristics a a. no heat sink, ta = 70c. this is an estimate based on a 4-layer pcb that conforms to eia/jesd51?7 (101.6 mm x 114.3 mm x 1.6 mm) and p = 1.2w continuous dissipation. characteristic value in still air ? ja (c/w) 44.88 ? jb (c/w) 1.20 ? jc (c/w) 0.20 ? jt (c/w) 0.04 ? jb (c/w) 14.21 maximum junction temperature t j (c) b b. absolute junction temperature limits maintained through active thermal monitoring and dynamic tx duty cycle limiting. 125 maximum power dissipation (w) 1.2 mechanical information broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 81 bcm43362 data sheet broadcom confidential section 16: mechanical information figure 28: 69-ball wlbga mechanical information ordering information broadcom ? ieee 802.11 b/g/n mac/baseband/radio + sdio february 13, 2015 ? 43362-ds106-r page 82 bcm43362 data sheet broadcom confidential section 17: ordering information part number package description operating ambient temperature BCM43362KUBG 69-ball wlbga halogen-free package (4.52 mm x 2.92 mm, 0.40 pitch) single-band ieee 802.11b/g/n 2.4 ghz wlan ?30c to +85c note: add a ?t? to the end of the part number to specify ?tape and reel?. phone: 949-926-5000 fax: 949-926-5203 e-mail: info@broadcom.com web: www.broadcom.com broadcom corporation 5300 california avenue irvine, ca 92617 ? 2015 by broadcom corporation. all rights reserved. 43362-ds106-r february 13, 2015 broadcom ? corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. information furnished by broadcom corporation is believed to be accurate and reliable. however, broadcom corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. bcm43362 data sheet ? |
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